PIC24F04KA200 Datasheet, PDF (3/26 Pages) Microchip Technology – Flash Programming Specifications

2.2 Memory Map
The program memory map extends from 000000h to
FFFFFEh. Code storage is located at the base of the
memory map, and supports up to about 1.38 K words
of instructions (about 4 Kbytes). Figure 2-2 depicts the
memory map.
Table 2-2 provides the program memory size and
number of program memory rows present in each
device variant.
The erase operation can be done on one word, half of
a row or one row at a time. The program operation can
be done only one word at a time.
The device Configuration registers are implemented
from location, F80000h to F80010h, and can be erased
or programmed one register at a time. Table 2-3 pro-
vides the implemented Configuration registers and
their locations.
Locations, FF0000h and FF0002h, are reserved for the
Device ID registers. These bits can be used by the
programmer to identify the device type that is being
programmed. See Section 4.0 “Device ID” for more
information. The Device ID registers read out normally
even after code protection is applied.
TABLE 2-2: PROGRAM MEMORY SIZES
Device
Program Memory
Upper Address
(Instruction Words)
Rows
PIC24F04KA200
AFEh (1.375K)
44
PIC24F04KA201
TABLE 2-3: CONFIGURATION REGISTER
LOCATIONS
Configuration Register
Address
FGS
FOSCSEL
FOSC
FWDT
FPOR
FICD
FDS
F80004
F80006
F80008
F8000A
F8000C
F8000E
F80010
PIC24FXXKA2XX
FIGURE 2-2:
PROGRAM MEMORY MAP
User Flash
Code Memory
(2816 x 24-bit)
000000h
000AFEh
Reserved
Reserved
Diagnostic Words
800000h
8007EEh
8007F0h
8007FEh
800800h
Reserved
Configuration Registers
F80000h
F80010h
Device ID
(2 x 16-bit)
Reserved
FEFFFEh
FF0000h
FF0002h
FF0004h
FFFFFEh
 2010 Microchip Technology Inc.
DS39991A-page 3