PIC24F04KA200 Datasheet, PDF (15/26 Pages) Microchip Technology – Flash Programming Specifications

PIC24FXXKA2XX
TABLE 3-8: PIC24FXXKA2XX FAMILY CONFIGURATION BITS DESCRIPTION
Bit Field
Register
Description
BOREN<1:0>
FPOR<1:0>
Brown-out Reset Enable bits
11 = Brown-out Reset is enabled in hardware; SBOREN bit is disabled
10 = Brown-out Reset is enabled only while device is active and disabled in
Sleep; SBOREN bit is disabled
01 = Brown-out Reset controlled with the SBOREN bit setting
00 = Brown-out Reset is disabled in hardware; SBOREN bit is disabled
BORV<1:0>
FPOR<6:5>
Brown-out Reset Voltage bits
11 = VBOR set to 1.8V min
10 = VBOR set to 2.0V min
01 = VBOR set to 2.7V min
00 = Downside protection on POR enabled – “Zero-power” selected
DSWDTEN
FDS<7>
Deep Sleep Watchdog Timer Enable bit
1 = DSWDT is enabled
0 = DSWDT is disabled
DSWDTPS<3:0> FDS<3:0>
Deep Sleep Watchdog Timer Postscale Select bits
The DSWDT prescaler is 32; this creates an approximate base time unit of
1 ms.
1111 = 1:2,147,483,648 (25.7 days)
1110 = 1:536,870,912 (6.4 days)
1101 = 1:134,217,728 (38.5 hours)
1100 = 1:33,554,432 (9.6 hours)
1011 = 1:8,388,608 (2.4 hours)
1010 = 1:2,097,152 (36 minutes)
1001 = 1:524,288 (9 minutes)
1000 = 1:131,072 (135 seconds)
0111 = 1:32,768 (34 seconds)
0110 = 1:8,192 (8.5 seconds)
0101 = 1:2,048 (2.1 seconds)
0100 = 1:512 (528 ms)
0011 = 1:128 (132 ms)
0010 = 1:32 (33 ms)
0001 = 1:8 (8.3 ms)
0000 = 1:2 (2.1 ms)
DSZPBOR
FDS<6>
Deep Sleep Zero-Power BOR Enable bit
1 = Zero-Power BOR is enabled in Deep Sleep
0 = Zero-Power BOR is disabled in Deep Sleep (does not affect operation in
non Deep Sleep modes)
FCKSM<1:0>
FOSC<7:6>
Clock Switching and Monitor Selection Configuration bits
1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
FNOSC<2:0>
FOSCSEL<2:0> Oscillator Selection bits
000 = Fast RC Oscillator (FRC)
001 = Fast RC Oscillator with divide-by-N with PLL module (FRCDIV+PLL)
010 = Primary Oscillator (XT, HS, EC)
011 = Primary Oscillator with PLL module (HS+PLL, EC+PLL)
100 = Secondary Oscillator (SOSC)
101 = Low-Power RC Oscillator (LPRC)
110 = Reserved; do not use
111 = Fast RC Oscillator with divide-by-N (FRCDIV)
Note 1: The MCLRE fuse can only be changed when using the VPP-Based Test mode entry. This prevents a user
from accidentally locking out the device from low-voltage test entry.
 2010 Microchip Technology Inc.
DS39991A-page 15