PIC24F04KA200 Datasheet, PDF (7/26 Pages) Microchip Technology – Flash Programming Specifications

PIC24FXXKA2XX
3.3 Entering ICSP Mode
3.3.1 LOW-VOLTAGE ICSP ENTRY
As illustrated in Figure 3-4, the following processes are
involved in entering ICSP Program/Verify mode using
MCLR:
1. MCLR is briefly driven high, then low.
2. A 32-bit key sequence is clocked into PGDx.
3. MCLR is then driven high within a specified
period of time and held.
The programming voltage, VIH, is applied to MCLR; this
is VDD in the case of PIC24FXXKA2XX devices. There
is no minimum time requirement for holding at VIH.
After VIH is removed, an interval of at least P18 must
elapse before presenting the key sequence on PGDx.
The key sequence is a specific 32-bit pattern:
‘0100 1101 0100 0011 0100 1000 0101
0001‘ (more easily remembered as 4D434851h in
hexadecimal). The device will enter Program/Verify
mode only if the sequence is valid. The Most Significant
bit (MSb) of the most significant nibble must be shifted in
first.
Once the key sequence is complete, VIH must be
applied to MCLR and held at that level for as long as
the Program/Verify mode is to be maintained. An
interval of at least P19 and P7 must elapse before
presenting data on PGDx. Signals appearing on PGCx
before P7 has elapsed would not be interpreted as
valid.
3.3.2 HIGH-VOLTAGE ICSP ENTRY
Entering the ICSP Program/Verify mode, using the VPP
pin is the same as entering the mode using MCLR. The
only difference is the programming voltage applied to
VPP is VIHH, and before presenting the key sequence
on PGDx, an interval of at least P18 should elapse (see
Figure 3-5).
Once the key sequence is complete, an interval of at
least P7 should elapse, and the voltage should remain
at VIHH. The voltage, VIHH, must be held at that level for
as long as the Program/Verify mode is to be main-
tained. An interval of at least P7 must elapse before
presenting the data on PGDx.
Signals appearing on PGDx before P7 has elapsed will
not be interpreted as valid.
Upon a successful entry, the program memory can be
accessed and programmed in serial fashion. While in
ICSP mode, all unused I/Os are placed in a
high-impedance state.
FIGURE 3-4:
P6
MCLR
ENTERING ICSP™ MODE USING LOW-VOLTAGE ENTRY
P14
VIH
P19 P7
VIH
VDD
PGDx
PGCx
Program/Verify Entry Code = 4D434851h
0 1 0 0 1 ... 0 0 0 1
b31 b30 b29 b28 b27
b3 b2 b1 b0
P18
P1A
P1B
FIGURE 3-5:
P6
VPP
VDD
PGDx
PGCx
ENTERING ICSP™ MODE USING HIGH-VOLTAGE ENTRY
VIHH
P7
VIH
Program/Verify Entry Code = 4D434851h
0 1 0 0 1 ... 0 0 0 1
b31 b30 b29 b28 b27
b3 b2 b1 b0
P18
P1A
P1B
 2010 Microchip Technology Inc.
DS39991A-page 7