MRF49XAT-I-ST Datasheet, PDF (71/102 Pages) Microchip Technology – ISM Band Sub-GHz RF Transceiver

MRF49XA
3.18.1 INTERRUPT MODE
The user can define the FIFO interrupt level (the
number of received bits) which generates the FINT
when the level is exceeded. In this case, the Status bits
report the changed FIFO status.
3.18.2 POLLING MODE
When the FSEL signal is low, the FIFO output is
connected directly to the SDO pin and its contents are
clocked out by the SCK pin. Set the FIFO interrupt level
to 1. In this case, as long as FINT indicates received
bits in the FIFO, the microcontroller continues to take
the bits away. When FINT goes low, no more bits need
to be taken.
An SPI read command (Receiver FIFO Read
Command) is also available to read out the contents of
the FIFO. See Figure 3-19 for a simple receiver FIFO
read, in Polling mode, on SPI lines.
TABLE 3-4:
Mode
Receive
RECEIVE PIN FUNCTION VS. OPERATION MODE
Bit Setting
Function
Pin 6
FIFOEN = 0
FIFOEN = 1
Receiver FIFO Disabled
Receiver FIFO Enabled
RX Data Output
FSEL Input
(RX data FIFO can be
accessed)
Pin 7
RX Data Clock Output
FINT Output
FIGURE 3-19:
FIFO READ EXAMPLE WITH FINT POLLING
CS
SCK
FSEL
SDO
0
1
2
3
4
FIFO OUT
FIFO Read Out
FO + 1 FO + 2 FO + 3
FO + 4
FINT
Note:
During FIFO access, fSCK cannot be
higher than fref/4, where fref is the crystal
oscillator frequency. If the duty cycle of
the clock signal is not 50%, the shorter
period of the clock pulse should be at
least 2/fref.
The registers associated with reception are:
• STSREG (see Register 2-1)
• GENCREG (see Register 2-2)
• RXCREG (see Register 2-7)
• FIFORSTREG (see Register 2-10)
• PMCREG (see Register 2-13)
© 2009-2011 Microchip Technology Inc.
Preliminary
DS70590C-page 71