MRF49XAT-I-ST Datasheet, PDF (29/102 Pages) Microchip Technology – ISM Band Sub-GHz RF Transceiver

MRF49XA
REGISTER 2-8: BBFCREG: BASEBAND FILTER CONFIGURATION REGISTER (POR: 0xC22C)
W-1
W-1
W-0
W-0
W-0
W-0
W-1
W-0
CCB<15:8>
bit 15
bit 8
W-0
W-0
W-1
W-0
W-1
ACRLC
MCRLC
r
FTYPE
r
bit 7
W-1
W-0
DQTI<2:0>
W-0
bit 0
Legend:
R = Readable bit
-n = Value at POR
r = reserved bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
CCB<15:8>: Command Code bits
The command code bits (11000010b) are serially sent to the microcontroller to identify the bits to be
written in the BBFCREG.
ACRLC: Automatic Clock Recovery Lock Control bit
1 = Configures the clock recovery lock control as automatic. In this setting, the clock recovery starts
in Fast mode and automatically switches to Slow mode after locking
0 = Clock recovery lock is controlled in Manual mode
MCRLC: Manual Clock Recovery Lock Control bit
1 = Configures the clock recovery lock control to Fast mode. Fast mode requires a preamble of at least
6-8 bits to determine the clock rate and then it locks.
0 = Configures the clock recovery lock control to Slow mode. Slow mode takes a bit longer period and
requires a preamble of at least 12-16 bits to determine the clock rate and then it locks. Slow mode
requires more accurate bit timing. See Register 2-12 for the relationship between data rate and
clock recovery.
Reserved: Write as ‘1’
FTYPE: Filter Type bit
1 = Configures the baseband filter as an analog RC low-pass filter
0 = Configures the baseband filter as a digital filter⁽¹⁾
Reserved: Write as ‘1’
DQTI<2:0>: Data Quality Threshold Indicator bits
The threshold parameter for the DQI should be set to less than four to report good signal quality if the
bit rate is close to the deviation. Usually, if the data rate falls less than the deviation, a higher threshold
parameter is permitted and might report a good signal quality⁽²⁾.
Note 1:
2:
The digital filter is a digital version of a simple RC low-pass filter followed by a comparator with hysteresis.
The time constant for the digital filter is automatically calculated based on the bit rate set in the DRSREG.
The bit rate in this mode should not exceed 115 kbps. In analog RC filter, the demodulator output is fed to
the RCLKOUT/FCAP/FINT pin over a 10 kΩ resistor. The filter cutoff frequency is set by the external
capacitor connected to this pin and VSS. Table 2-6 shows the optimum filter capacitor values for different
data rates.
The DQI parameter is calculated using Equation 2-3. The DQI parameter in BBFCREG should be chosen
according to the following rules:
- The parameter should be > 4, otherwise, noise might be treated as a valid FSK signal.
- The maximum value is 7.
© 2009-2011 Microchip Technology Inc.
Preliminary
DS70590C-page 29