MRF49XAT-I-ST Datasheet, PDF (41/102 Pages) Microchip Technology – ISM Band Sub-GHz RF Transceiver

MRF49XA
REGISTER 2-17: PLLCREG: PLL CONFIGURATION REGISTER (POR: 0xCC77)
W-1
W-1
W-0
W-0
W-1
W-1
W-0
CCB<15:8>
bit 15
W-0
bit 8
W-0
—
bit 7
W-1
W-1
CBTC<1:0>
W-1
W-0
W-1
r
PDDS
PLLDD
W-1
W-1
r
PLLBWB
bit 0
Legend:
R = Readable bit
-n = Value at POR
r = reserved bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
bit 7
bit 6-5
bit 4
bit 3
bit 2
bit 1
bit 0
CCB<15:8>: Command Code bits
The command code bits (11001100b) are serially sent to the microcontroller to identify the bits to be
written in the PLLCREG.
Unimplemented: Write as ‘0’
CBTC<1:0>: Clock Buffer Time Control bits
These bits control the rise and fall time for the clock buffer which is dependant on the output clock
frequency from the BCSREG.
11 = 5 MHz - 10 MHz
10 = 3.3 MHz
01 = 2.5 MHz or less
00 = 2.5 MHz or less
Reserved: Masked to ‘1’
PDDS: Phase Detector Delay Switch bit
1 = Enables the phase detector delay function
0 = Disables the phase detector delay function
PLLDD: PLL Dithering Disable bit
1 = Disables PLL dithering
0 = Enables PLL dithering
Reserved: Write as ‘1’
PLLBWB: PLL Bandwidth bit
Enabling the bit configures higher data rates, faster settling and reduced phase noise; thus, resulting
in a better RF performance.
1 = -102 dBc/Hz, > 90 kbps (max 256 kbps)
0 = -107 dBc/Hz, < 90 kbps (max 86.2 kbps)
© 2009-2011 Microchip Technology Inc.
Preliminary
DS70590C-page 41