MRF49XAT-I-ST Datasheet, PDF (17/102 Pages) Microchip Technology – ISM Band Sub-GHz RF Transceiver

MRF49XA
2.14 Receive FIFO
The received data in MRF49XA is filled into a 16-bit First
In First Out (FIFO) register. The FIFO is configured to
generate an interrupt after receiving a defined number of
bits. When the internal FIFO is enabled, the FIFO
interrupt pin (RCLKOUT/FCAP/FINT) acts as a FIFO full
interrupt, indicating that the FIFO has been filled to its
preprogrammed limit. The receiver starts filling FIFO
with data when it identifies the synchronous pattern
through the synchronous pattern recognition circuit.
During this process, the FINTDIO bit changes its state.
The FIFO interrupt level is programmable from 1 to 16
bits. It is recommended to set the threshold to at least
half the length of the register (8 bits) to ensure that the
external host microcontroller has time to set up. The
synchronous pattern recognition circuit prevents the
FIFO from being filled up with noise, and hence, avoids
overloading the external host microcontroller.
Note: The synchronous word is not accessible in
the RX FIFO. The SYNBREG provides this
information to the host microcontroller.
The FIFO read clock (SCK) must be < fXTAL/4 or
< 2.5 MHz for 10 MHz on RFXTAL. The
FSK/DATA/FSEL as the FIFO select pin, selects the
FIFO and the first bit appears on the next clock when
reading the RXFIFOREG.
In hardware, the FSK/DATA/FSEL pin is configured as
DATA (Data In) and with internal TXBREG disabled;
this manually modulates the data from the external host
microcontroller. If the TXBREG is enabled, this pin can
be tied “high” or can be left unconnected.
The internal synchronous pattern and the pattern
length are user-programmable. If the Chip Select (CS)
pin is low, the data bits on the SDI pin are shifted into
the device on the rising edge of the clock on the SCK
pin.The serial interface is initialized if the CS signal is
high.
2.15 Serial Peripheral Interface
The MRF49XA communicates with the host
microcontroller through a 4-wire SPI port as a slave
device. An SPI compatible serial interface lets the user
select, command and monitor the status of the
MRF49XA through the host microcontroller. All registers
consist of a command code, followed by a varying
number of parameter or data bits. As the device uses
word writes, the CS pin should be pulled low for 16 bits.
Data bits on the SDI pin are shifted into the device upon
the rising edge of the clock on the SCK pin whenever the
CS pin is low.
The maximum clock frequency for the SPI bus is
20 MHz. The MRF49XA supports SPI mode 0,0 which
requires the SCK to remain Idle in a low state. The CS
pin must be held low to enable communication between
the host microcontroller and the MRF49XA. The
device’s timing specification details are given in
Table 5-8. Data is received by the transceiver through
the SDI pin and is clocked on the rising edge of SCK.
The timing diagram is shown in Figure 5-1. MRF49XA
sends out the data through the SDO pin and is clocked
out on the falling edge of SCK. The Most Significant
bit (MSb) is sent first (e.g., bit 15 for a 16-bit command)
in any data. The POR circuit sets default values in all
control and command registers.
Note:
Special care must be taken when the
microcontroller’s built-in hardware serial port
is used. If the port cannot be switched to a
16-bit mode, then a separate I/O line should
be used to control the CS pin to ensure a low
level during the complete duration of the
communication (command) or a software
serial control interface should be
implemented.
The SDO pin defaults to a low state when the CS pin is
high (the MRF49XA is not selected). This pin has a
tri-state buffer and uses a bus hold logic. For the SPI
interface, see Figure 4-1.
The following parameters can be programmed and set
through SPI:
• Frequency band
• Center frequency of the synthesizer
• Division ratio for the microcontroller clock
• Wake-up timer period
• Bandwidth of the baseband signal path
• Low supply voltage detector threshold
Any of these auxiliary functions can be disabled when
not required. After power-on, all parameters are set to
default values. The programmed values are retained
during Sleep mode. The interface supports the read out
of a status register which provides detailed information
about the status of the transceiver and the received
data.
Note:
To test the SPI interface lines, set the LBD
(Low Battery Detector) threshold below the
actual VDD and the device must generate
an interrupt.
© 2009-2011 Microchip Technology Inc.
Preliminary
DS70590C-page 17