PIC16F819T-E Datasheet, PDF (65/176 Pages) Microchip Technology – 18/20-Pin Enhanced Flash Microcontrollers with nanoWatt Technology

8.0 TIMER2 MODULE
Timer2 is an 8-bit timer with a prescaler and a
postscaler. It can be used as the PWM time base for the
PWM mode of the CCP1 module. The TMR2 register is
readable and writable and is cleared on any device
Reset.
The input clock (FOSC/4) has a prescale option of 1:1,
1:4 or 1:16, selected by control bits,
T2CKPS1:T2CKPS0 (T2CON<1:0>).
The Timer2 module has an 8-bit period register, PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
initialized to FFh upon Reset.
The match output of TMR2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a TMR2 interrupt (latched in flag bit,
TMR2IF (PIR1<1>)).
Timer2 can be shut-off by clearing control bit, TMR2ON
(T2CON<2>), to minimize power consumption.
Register 8-1 shows the Timer2 Control register.
Additional information on timer modules is available in
the “PICmicro^® Mid-Range MCU Family Reference
Manual” (DS33023).
PIC16F818/819
8.1 Timer2 Prescaler and Postscaler
The prescaler and postscaler counters are cleared
when any of the following occurs:
• A write to the TMR2 register
• A write to the T2CON register
• Any device Reset (Power-on Reset, MCLR, WDT
Reset or Brown-out Reset)
TMR2 is not cleared when T2CON is written.
8.2 Output of TMR2
The output of TMR2 (before the postscaler) is fed to the
Synchronous Serial Port module which optionally uses
it to generate a shift clock.
FIGURE 8-1:
TIMER2 BLOCK DIAGRAM
Sets Flag
bit TMR2IF
TMR2
Output⁽¹⁾
Reset
TMR2 reg
Postscaler
Comparator
1:1 to 1:16 _EQ
4
PR2 reg
Prescaler
1:1, 1:4, 1:16 ^FOSC/4
2
Note 1: TMR2 register output can be software
selected by the SSP module as a baud clock.
 2004 Microchip Technology Inc.
DS39598E-page 63