PIC16F819T-E Datasheet, PDF (17/176 Pages) Microchip Technology – 18/20-Pin Enhanced Flash Microcontrollers with nanoWatt Technology

PIC16F818/819
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Detailson
POR, BOR page:
Bank 2
100h⁽¹⁾ INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
23
101h TMR0
Timer0 Module Register
xxxx xxxx
53
102h⁽¹ PCL
Program Counter’s (PC) Least Significant Byte
0000 0000
23
103h⁽¹⁾ STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx
16
104h⁽¹⁾ FSR
Indirect Data Memory Address Pointer
xxxx xxxx
23
105h
—
Unimplemented
—
—
106h PORTB
PORTB Data Latch when written; PORTB pins when read
xxxx xxxx
43
107h
—
Unimplemented
—
—
108h
—
Unimplemented
—
—
109h
—
10Ah^(1,2) PCLATH
10Bh⁽¹⁾ INTCON
Unimplemented
—
—
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
23
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF 0000 000x
18
10Ch EEDATA
EEPROM/Flash Data Register Low Byte
xxxx xxxx
25
10Dh EEADR
EEPROM/Flash Address Register Low Byte
xxxx xxxx
25
10Eh EEDATH
—
— EEPROM/Flash Data Register High Byte
--xx xxxx
25
10Fh EEADRH
—
—
—
—
—
EEPROM/Flash Address Register ---- -xxx
25
High Byte
Bank 3
180h⁽¹⁾ INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
23
181h OPTION_REG RBPU INTEDG T0CS
T0SE
PSA
PS2
PS1
PS0 1111 1111 17, 54
182h⁽¹⁾ PCL
Program Counter’s (PC) Least Significant Byte
0000 0000
23
183h⁽¹⁾ STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx
16
184h⁽¹⁾ FSR
Indirect Data Memory Address Pointer
xxxx xxxx
23
185h
—
Unimplemented
—
—
186h TRISB
PORTB Data Direction Register
1111 1111
43
187h
—
Unimplemented
—
—
188h
—
Unimplemented
—
—
189h
—
18Ah^(1,2) PCLATH
18Bh⁽¹⁾ INTCON
Unimplemented
—
—
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
23
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF 0000 000x
18
18Ch EECON1
EEPGD
—
—
FREE
WRERR WREN
WR
RD
x--x x000
26
18Dh EECON2
EEPROM Control Register 2 (not a physical register)
---- ----
25
18Eh
—
Reserved; maintain clear
0000 0000
—
18Fh
—
Reserved; maintain clear
0000 0000
—
Legend:
Note 1:
2:
3:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
These registers can be addressed from any bank.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are
transferred to the upper byte of the program counter.
Pin 5 is an input only; the state of the TRISA5 bit has no effect and will always read ‘1’.
 2004 Microchip Technology Inc.
DS39598E-page 15