PIC16F819T-E Datasheet, PDF (12/176 Pages) Microchip Technology – 18/20-Pin Enhanced Flash Microcontrollers with nanoWatt Technology

PIC16F818/819
2.2 Data Memory Organization
The data memory is partitioned into multiple banks that
contain the General Purpose Registers and the Special
Function Registers. Bits RP1 (Status<6>) and RP0
(Status<5>) are the bank select bits.
RP1:RP0
00
01
10
11
Bank
0
1
2
3
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Regis-
ters are the General Purpose Registers, implemented
as static RAM. All implemented banks contain SFRs.
Some “high use” SFRs from one bank may be mirrored
in another bank for code reduction and quicker access
(e.g., the Status register is in Banks 0-3).
Note:
EEPROM data memory description can be
found in Section 3.0 “Data EEPROM and
Flash Program Memory” of this data
sheet.
2.2.1
GENERAL PURPOSE REGISTER
FILE
The register file can be accessed either directly or
indirectly through the File Select Register, FSR.
DS39598E-page 10
 2004 Microchip Technology Inc.