DSPIC30F2010_08 Datasheet, PDF (65/204 Pages) Microchip Technology – High-Performance, 16-bit Digital Signal Controllers

10.4 Timer Interrupt
The 16-bit timer has the ability to generate an interrupt
on period match. When the timer count matches the
period register, the T1IF bit is asserted and an interrupt
will be generated, if enabled. The T1IF bit must be
cleared in software. The timer interrupt flag T1IF is
located in the IFS0 control register in the Interrupt
Controller.
When the Gated Time Accumulation mode is enabled,
an interrupt will also be generated on the falling edge of
the gate signal (at the end of the accumulation cycle).
Enabling an interrupt is accomplished via the
respective timer interrupt enable bit, T1IE. The timer
interrupt enable bit is located in the IEC0 control
register in the Interrupt Controller.
10.5 Real-Time Clock
Timer1, when operating in Real-Time Clock (RTC)
mode, provides time-of-day and event time stamping
capabilities. Key operational features of the RTC are:
• Operation from 32 kHz LP oscillator
• 8-bit prescaler
• Low power
• Real-Time Clock Interrupts
• These Operating modes are determined by
setting the appropriate bit(s) in the T1CON
Control register
FIGURE 10-2:
RECOMMENDED
COMPONENTS FOR
TIMER1 LP OSCILLATOR
RTC
C1
SOSCI
32.768 kHz
XTAL
dsPIC30F2010
SOSCO
C2
R
C1 = C2 = 18 pF; R = 100K
dsPIC30F2010
10.5.1 RTC OSCILLATOR OPERATION
When the TON = 1, TCS = 1 and TGATE = 0, the timer
increments on the rising edge of the 32 kHz LP
oscillator output signal, up to the value specified in the
period register, and is then Reset to ‘0’.
The TSYNC bit must be asserted to a logic ‘0’
(Asynchronous mode) for correct operation.
Enabling LPOSCEN (OSCCON<1>) will disable the
normal Timer and Counter modes, and enable a timer
carry-out wake-up event.
When the CPU enters Sleep mode, the RTC will
continue to operate, provided the 32 kHz external
crystal oscillator is active and the control bits have not
been changed. The TSIDL bit should be cleared to ‘0’
in order for RTC to continue operation in Idle mode.
10.5.2 RTC INTERRUPTS
When an interrupt event occurs, the respective
interrupt flag, T1IF, is asserted and an interrupt will be
generated, if enabled. The T1IF bit must be cleared in
software. The respective Timer interrupt flag, T1IF, is
located in the IFS0 status register in the Interrupt
Controller.
Enabling an interrupt is accomplished via the
respective timer interrupt enable bit, T1IE. The Timer
interrupt enable bit is located in the IEC0 control
register in the Interrupt Controller.
© 2008 Microchip Technology Inc.
DS70118H-page 65