DSPIC30F2010_08 Datasheet, PDF (196/204 Pages) Microchip Technology – High-Performance, 16-bit Digital Signal Controllers

dsPIC30F2010
Spaces ........................................................................ 28
Width ........................................................................... 28
Data EEPROM Memory ...................................................... 51
Erasing ........................................................................ 52
Erasing, Block ............................................................. 52
Erasing, Word ............................................................. 52
Protection Against Spurious Write .............................. 54
Reading....................................................................... 51
Write Verify ................................................................. 54
Writing ......................................................................... 53
Writing, Block .............................................................. 54
Writing, Word .............................................................. 53
DC Characteristics ............................................................ 149
BOR .......................................................................... 156
Brown-out Reset ....................................................... 155
I/O Pin Input Specifications ....................................... 153
I/O Pin Output Specifications .................................... 155
Idle Current (IIDLE) .................................................... 152
Operating Current (IDD)............................................. 151
Power-Down Current (IPD) ........................................ 153
Program and EEPROM............................................. 156
Temperature and Voltage Specifications .................. 149
Dead-Time Generators ....................................................... 88
Ranges........................................................................ 88
Development Support ....................................................... 145
Device Configuration
Register Map............................................................. 135
Device Configuration Registers......................................... 134
FBORPOR ................................................................ 134
FGS........................................................................... 134
FOSC ........................................................................ 134
FWDT........................................................................ 134
Device Overview ................................................................... 7
Divide Support..................................................................... 14
DSP Engine......................................................................... 15
Multiplier...................................................................... 17
Dual Output Compare Match Mode .................................... 74
Continuous Pulse Mode .............................................. 74
Single Pulse Mode ...................................................... 74
E
Edge-Aligned PWM............................................................. 87
Electrical Characteristics................................................... 149
AC ............................................................................. 157
DC ............................................................................. 149
Equations
A/D Conversion Clock ............................................... 115
Baud Rate ................................................................. 109
PWM Period ................................................................ 86
PWM Period (Up/Down Count Mode) ......................... 86
PWM Resolution ......................................................... 86
Serial Clock Rate ...................................................... 102
Errata .................................................................................... 6
Exception Sequence
Trap Sources .............................................................. 41
External Clock Timing Characteristics
Type A and B Timer .................................................. 165
External Clock Timing Requirements................................ 158
Type A Timer ............................................................ 165
Type B Timer ............................................................ 166
Type C Timer ............................................................ 166
External Interrupt Requests ................................................ 43
F
Fast Context Saving............................................................ 43
Firmware Instructions........................................................ 137
DS70118H-page 196
Flash Program Memory ...................................................... 45
In-Circuit Serial Programming (ICSP)......................... 45
Run-Time Self-Programming (RTSP) ......................... 45
Table Instruction Operation Summary ........................ 45
I
I/O Pin Specifications
Input.......................................................................... 153
Output ....................................................................... 155
I/O Ports.............................................................................. 55
Parallel I/O (PIO) ........................................................ 55
I²C....................................................................................... 97
I²C 10-bit Slave Mode Operation........................................ 99
Reception ................................................................. 100
Transmission ............................................................ 100
I²C 7-bit Slave Mode Operation.......................................... 99
Reception ................................................................... 99
Transmission .............................................................. 99
I²C Master Mode
Baud Rate Generator ............................................... 102
Clock Arbitration ....................................................... 102
Multi-Master Communication, Bus Collision and
Bus Arbitration .................................................. 102
Reception ................................................................. 102
Transmission ............................................................ 102
I²C Module
Addresses................................................................... 99
Bus Data Timing Characteristics
Master Mode..................................................... 178
Slave Mode....................................................... 180
Bus Data Timing Requirements
Master Mode..................................................... 179
Slave Mode....................................................... 181
Bus Start/Stop Bits Timing Characteristics
Master Mode..................................................... 178
Slave Mode....................................................... 180
General Call Address Support .................................. 101
Interrupts .................................................................. 101
IPMI Support............................................................. 101
Master Operation ...................................................... 102
Master Support ......................................................... 101
Operating Function Description .................................. 97
Operation During CPU Sleep and Idle Modes .......... 103
Pin Configuration ........................................................ 97
Programmer’s Model .................................................. 97
Register Map ............................................................ 104
Registers .................................................................... 97
Slope Control ............................................................ 101
Software Controlled Clock Stretching (STREN = 1) . 101
Various Modes............................................................ 97
Idle Current (IIDLE) ............................................................ 152
In-Circuit Serial Programming (ICSP)............................... 123
Independent PWM Output .................................................. 89
Initialization Condition for RCON Register Case 1 ........... 132
Initialization Condition for RCON Register Case 2 ........... 132
Initialization Condition for RCON Register, Case 1 .......... 132
Input Capture (CAPx) Timing Characteristics................... 168
Input Capture Interrupts...................................................... 71
Register Map .............................................................. 72
Input Capture Module ......................................................... 69
In CPU Sleep Mode .................................................... 71
Simple Capture Event Mode....................................... 70
Input Capture Timing Requirements................................. 168
Input Change Notification Module....................................... 56
Register Map (bits 15-0) ............................................. 57
Input Characteristics
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