DSPIC30F2010_08 Datasheet, PDF (133/204 Pages) Microchip Technology – High-Performance, 16-bit Digital Signal Controllers

19.4 Watchdog Timer (WDT)
19.4.1 WATCHDOG TIMER OPERATION
The primary function of the Watchdog Timer (WDT) is
to reset the processor in the event of a software
malfunction. The WDT is a free running timer, which
runs off an on-chip RC oscillator, requiring no external
component. Therefore, the WDT timer will continue to
operate even if the main processor clock (e.g., the
crystal oscillator) fails.
19.4.2 ENABLING AND DISABLING THE
WDT
The Watchdog Timer can be “Enabled” or “Disabled”
only through a Configuration bit (FWDTEN) in the
Configuration register FWDT.
Setting FWDTEN = 1 enables the Watchdog Timer.
The enabling is done when programming the device.
By default, after chip-erase, FWDTEN bit = 1. Any
device programmer capable of programming
dsPIC30F devices allows programming of this and
other Configuration bits.
If enabled, the WDT will increment until it overflows or
“times out”. A WDT time-out will force a device Reset
(except during Sleep). To prevent a WDT time-out, the
user must clear the Watchdog Timer using a CLRWDT
instruction.
If a WDT times out during Sleep, the device will
wake-up. The WDTO bit in the RCON register will be
cleared to indicate a wake-up resulting from a WDT
time-out.
Setting FWDTEN = 0 allows user software to
enable/disable the Watchdog Timer via the SWDTEN
(RCON<5>) control bit.
19.5 Power-Saving Modes
There are two power-saving states that can be entered
through the execution of a special instruction, PWRSAV.
These are: Sleep and Idle.
The format of the PWRSAV instruction is as follows:
PWRSAV <parameter>, where ‘parameter’ defines
Idle or Sleep mode.
19.5.1 SLEEP MODE
In Sleep mode, the clock to the CPU and peripherals is
shutdown. If an on-chip oscillator is being used, it is
shutdown.
The fail-safe clock monitor is not functional during
Sleep, since there is no clock to monitor. However,
LPRC clock remains active if WDT is operational during
Sleep.
The Brown-out protection circuit and the Low Voltage
Detect circuit, if enabled, will remain functional during
Sleep.
dsPIC30F2010
The processor wakes up from Sleep if at least one of
the following conditions has occurred:
• any interrupt that is individually enabled and meets
the required priority level
• any Reset (POR, BOR and MCLR)
• WDT time-out
On waking up from Sleep mode, the processor will restart
the same clock that was active prior to entry into Sleep
mode. When clock switching is enabled, bits
COSC<1:0> will determine the oscillator source that will
be used on wake-up. If clock switch is disabled, then
there is only one system clock.
Note:
If a POR or BOR occurred, the selection of
the oscillator is based on the FOS<1:0>
and FPR<3:0> Configuration bits.
If the clock source is an oscillator, the clock to the device
will be held off until OST times out (indicating a stable
oscillator). If PLL is used, the system clock is held off
until LOCK = 1 (indicating that the PLL is stable). In either
case, TPOR, TLOCK and TPWRT delays are applied.
If EC, FRC, LPRC or ERC oscillators are used, then a
delay of TPOR (~ 10 μs) is applied. This is the smallest
delay possible on wake-up from Sleep.
Moreover, if LP oscillator was active during Sleep, and
LP is the oscillator used on wake-up, then the start-up
delay will be equal to TPOR. PWRT delay and OST timer
delay are not applied. In order to have the smallest pos-
sible start-up delay when waking up from Sleep, one of
these faster wake-up options should be selected before
entering Sleep.
Any interrupt that is individually enabled (using the
corresponding IE bit) and meets the prevailing priority
level will be able to wake-up the processor. The
processor will process the interrupt and branch to the
ISR. The Sleep status bit in RCON register is set upon
wake-up.
Note:
In spite of various delays applied (TPOR,
TLOCK and TPWRT), the crystal oscillator
(and PLL) may not be active at the end of
the time-out (e.g., for low-frequency
crystals. In such cases), if FSCM is
enabled, then the device will detect this as
a clock failure and process the clock
failure trap, the FRC oscillator will be
enabled, and the user will have to
re-enable the crystal oscillator. If FSCM is
not enabled, then the device will simply
suspend execution of code until the clock
is stable, and will remain in Sleep until the
oscillator clock has started.
© 2008 Microchip Technology Inc.
DS70118H-page 133