DSPIC30F2010_08 Datasheet, PDF (103/204 Pages) Microchip Technology – High-Performance, 16-bit Digital Signal Controllers

If a Start, Restart, Stop or Acknowledge condition was
in progress when the bus collision occurred, the
condition is aborted, the SDA and SCL lines are
de-asserted, and the respective control bits in the
I2CCON register are cleared to ‘0’. When the user
services the bus collision Interrupt Service Routine,
and if the I²C bus is free, the user can resume
communication by asserting a Start condition.
The Master will continue to monitor the SDA and SCL
pins, and if a Stop condition occurs, the MI2CIF bit will
be set.
A write to the I2CTRN will start the transmission of data
at the first data bit, regardless of where the transmitter
left off when bus collision occurred.
In a Multi-Master environment, the interrupt generation
on the detection of Start and Stop conditions allows the
determination of when the bus is free. Control of the I²C
bus can be taken when the P bit is set in the I2CSTAT
register, or the bus is Idle and the S and P bits are
cleared.
dsPIC30F2010
16.13 I²C Module Operation During CPU
Sleep and Idle Modes
16.13.1 I²C OPERATION DURING CPU
SLEEP MODE
When the device enters Sleep mode, all clock sources
to the module are shutdown and stay at logic ‘0’. If
Sleep occurs in the middle of a transmission, and the
state machine is partially into a transmission as the
clocks stop, then the transmission is aborted. Similarly,
if Sleep occurs in the middle of a reception, then the
reception is aborted.
16.13.2 I²C OPERATION DURING CPU IDLE
MODE
For the I²C, the I2CSIDL bit selects if the module will
stop on Idle or continue on Idle. If I2CSIDL = 0, the
module will continue operation on assertion of the Idle
mode. If I2CSIDL = 1, the module will stop on Idle.
© 2008 Microchip Technology Inc.
DS70118H-page 103