DSPIC30F2010_08 Datasheet, PDF (115/204 Pages) Microchip Technology – High-Performance, 16-bit Digital Signal Controllers

18.4 Programming the Start of
Conversion Trigger
The conversion trigger will terminate acquisition and
start the requested conversions.
The SSRC<2:0> bits select the source of the
conversion trigger.
The SSRC bits provide for up to five alternate sources
of conversion trigger.
When SSRC<2:0> = 000, the conversion trigger is
under software control. Clearing the SAMP bit will
cause the conversion trigger.
When SSRC<2:0> = 111 (Auto-Start mode), the
conversion trigger is under A/D clock control. The
SAMC bits select the number of A/D clocks between
the start of acquisition and the start of conversion. This
provides the fastest conversion rates on multiple
channels. SAMC must always be at least one clock
cycle.
Other trigger sources can come from timer modules,
Motor Control PWM module or external interrupts.
Note:
To operate the A/D at the maximum
specified conversion speed, the Auto
Convert Trigger option should be selected
(SSRC = 111) and the Auto Sample Time
bits should be set to 1 TAD
(SAMC = 00001). This configuration will
give a total conversion period (sample +
convert) of 13 TAD.
The use of any other conversion trigger
will result in additional TAD cycles to
synchronize the external event to the A/D.
18.5 Aborting a Conversion
Clearing the ADON bit during a conversion will abort
the current conversion and stop the sampling
sequencing. The ADCBUF will not be updated with the
partially completed A/D conversion sample. That is, the
ADCBUF will continue to contain the value of the last
completed conversion (or the last value written to the
ADCBUF register).
If the clearing of the ADON bit coincides with an auto
start, the clearing has a higher priority.
After the A/D conversion is aborted, a 2 TAD wait is
required before the next sampling may be started by
setting the SAMP bit.
If sequential sampling is specified, the A/D will continue
at the next sample pulse which corresponds with the
next channel converted. If simultaneous sampling is
specified, the A/D will continue with the next
multichannel group conversion sequence.
dsPIC30F2010
18.6 Selecting the A/D Conversion
Clock
The A/D conversion requires 12 TAD. The source of the
A/D conversion clock is software selected using a 6-bit
counter. There are 64 possible options for TAD.
EQUATION 18-1: A/D CONVERSION CLOCK
TAD = TCY * (0.5 * (ADCS<5:0> + 1))
TAD
ADCS<5:0> = 2 _TCY – 1
The internal RC oscillator is selected by setting the
ADRC bit.
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
of 83.33 nsec (for VDD = 5V). Refer to Section 22.0
"Electrical Characteristics" for minimum TAD under
other operating conditions.
Example 18-1 shows a sample calculation for the
ADCS<5:0> bits, assuming a device operating speed
of 30 MIPS.
EXAMPLE 18-1: A/D CONVERSION CLOCK
CALCULATION
TAD = 84 nsec
TCY = 33 nsec (30 MIPS)
ADCS<5:0> = 2
TAD
TCY
–1
= 2 • ^{84 nsec} – 1
33 nsec
= 4.09
Therefore,
Set ADCS<5:0> = 5
Actual TAD =
TCY
2
(ADCS<5:0> + 1)
= ^{33 nsec} (5 + 1)
2
= 99 nsec
© 2008 Microchip Technology Inc.
DS70118H-page 115