PIC16F1938 Datasheet, PDF(39/452 Page) Microchip Technology – 28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers

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PIC16F1938 Datasheet, PDF (39/452 Pages) Microchip Technology – 28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers

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PIC16(L)F1938/9

TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Value on all

other

Resets

Bank 3

180h(2) INDF0

Addressing this location uses contents of FSR0H/FSR0L to Address Data Memory

(not a physical register)

xxxx xxxx xxxx xxxx

181h(2) INDF1

Addressing this location uses contents of FSR1H/FSR1L to Address Data Memory

(not a physical register)

xxxx xxxx xxxx xxxx

182h(2) PCL

Program Counter (PC) Least Significant Byte

0000 0000 0000 0000

183h(2) STATUS

â

â

â

TO

PD

Z

DC

C

---1 1000 ---q quuu

184h(2) FSR0L

Indirect Data Memory Address 0 Low Pointer

0000 0000 uuuu uuuu

185h(2) FSR0H

Indirect Data Memory Address 0 High Pointer

0000 0000 0000 0000

186h(2) FSR1L

Indirect Data Memory Address 1 Low Pointer

0000 0000 uuuu uuuu

187h(2) FSR1H

Indirect Data Memory Address 1 High Pointer

0000 0000 0000 0000

188h(2) BSR

â

â

â

BSR<4:0>

---0 0000 ---0 0000

189h(2) WREG

Working Register

0000 0000 uuuu uuuu

18Ah(1, 2) PCLATH

â

Write Buffer for the upper 7 bits of the Program Counter

-000 0000 -000 0000

18Bh(2) INTCON

GIE

PEIE

TMR0IE

INTE

IOCIE

TMR0IF

INTF

IOCIF 0000 0000 0000 0000

18Ch

ANSELA

â

â

ANSA5

ANSA4

ANSA3

ANSA2 ANSA1 ANSA0 --11 1111 --11 1111

18Dh

ANSELB

â

â

ANSB5

ANSB4

ANSB3

ANSB2 ANSB1 ANSB0 --11 1111 --11 1111

18Eh

â

Unimplemented

â

â

18Fh(3) ANSELD

ANSD7

ANSD6

ANSD5

ANSD4

ANSD3

ANSD2 ANSD1 ANSD0 1111 1111 1111 1111

190h(3) ANSELE

â

â

â

â

â

ANSE2 ANSE1 ANSE0 ---- -111 ---- -111

191h

EEADRL

EEPROM / Program Memory Address Register Low Byte

0000 0000 0000 0000

192h

EEADRH

â

EEPROM / Program Memory Address Register High Byte

-000 0000 -000 0000

193h

EEDATL

EEPROM / Program Memory Read Data Register Low Byte

xxxx xxxx uuuu uuuu

194h

EEDATH

â

â

EEPROM / Program Memory Read Data Register High Byte

--xx xxxx --uu uuuu

195h

EECON1

EEPGD

CFGS

LWLO

FREE

WRERR

WREN

WR

RD 0000 x000 0000 q000

196h

EECON2

EEPROM control register 2

0000 0000 0000 0000

197h

â

Unimplemented

â

â

198h

â

Unimplemented

â

â

199h

RCREG

USART Receive Data Register

0000 0000 0000 0000

19Ah

TXREG

USART Transmit Data Register

0000 0000 0000 0000

19Bh

SPBRGL

BRG<7:0>

0000 0000 0000 0000

19Ch

SPBRGH

BRG<15:8>

0000 0000 0000 0000

19Dh

RCSTA

SPEN

RX9

SREN

CREN

ADDEN

FERR

OERR

RX9D 0000 000x 0000 000x

19Eh

TXSTA

CSRC

TX9

TXEN

SYNC

SENDB

BRGH

TRMT

TX9D 0000 0010 0000 0010

19Fh

BAUDCON

ABDOVF RCIDL

â

SCKP

BRG16

â

WUE ABDEN 01-0 0-00 01-0 0-00

Legend:

Note 1:

2:

3:

4:

x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as â0â, r = reserved.

Shaded locations are unimplemented, read as â0â.

The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred

to the upper byte of the program counter.

These registers can be addressed from any bank.

These registers/bits are not implemented on PIC16(L)F1938 devices, read as â0â.

Unimplemented, read as â1â.

ï£ 2011 Microchip Technology Inc.

Preliminary

DS41574A-page 39

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