PIC16F1938 Datasheet, PDF (313/452 Pages) Microchip Technology – 28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers

PIC16(L)F1938/9
FIGURE 25-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
RX/DT
pin
TX/CK pin
(SCKP = 0)
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
TX/CK pin
(SCKP = 1)
Write to
bit SREN
SREN bit
CREN bit ^{‘0’}
‘0’
RCIF bit
(Interrupt)
Read
RXREG
Note:
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
TABLE 25-8: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER
RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
BAUDCON ABDOVF RCIDL
—
SCKP BRG16
—
WUE ABDEN
300
INTCON
GIE
PEIE TMR0IE INTE
IOCIE TMR0IF INTF
IOCIF
94
PIE1
PIR1
TMR1GIE ADIE
RCIE
TXIE SSPIE CCP1IE TMR2IE TMR1IE
95
TMR1GIF ADIF
RCIF
TXIF
SSPIF CCP1IF TMR2IF TMR1IF
98
RCREG
RCSTA
EUSART Receive Data Register
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
294*
299
SPBRGL
BRG<7:0>
301*
SPBRGH
TRISC
BRG<15:8>
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
301*
138
TXSTA
CSRC
TX9
TXEN SYNC SENDB BRGH TRMT TX9D
298
Legend: — = unimplemented read as ‘0’. Shaded cells are not used for synchronous master reception.
* Page provides register information.
 2011 Microchip Technology Inc.
Preliminary
DS41574A-page 313