PIC16LF877A-I Datasheet, PDF (29/234 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers

PIC16F87XA
2.2.2.6 PIE2 Register
The PIE2 register contains the individual enable bits for
the CCP2 peripheral interrupt, the SSP bus collision
interrupt, EEPROM write operation interrupt and the
comparator interrupt.
Note: Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
REGISTER 2-6:
PIE2 REGISTER (ADDRESS 8Dh)
U-0
R/W-0
U-0
R/W-0
—
CMIE
—
EEIE
bit 7
R/W-0
BCLIE
U-0
U-0
R/W-0
—
—
CCP2IE
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-1
bit 0
Unimplemented: Read as ‘0’
CMIE: Comparator Interrupt Enable bit
1 = Enables the comparator interrupt
0 = Disable the comparator interrupt
Unimplemented: Read as ‘0’
EEIE: EEPROM Write Operation Interrupt Enable bit
1 = Enable EEPROM write interrupt
0 = Disable EEPROM write interrupt
BCLIE: Bus Collision Interrupt Enable bit
1 = Enable bus collision interrupt
0 = Disable bus collision interrupt
Unimplemented: Read as ‘0’
CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
 2003 Microchip Technology Inc.
DS39582B-page 27