PIC16LF877A-I Datasheet, PDF (21/234 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers

PIC16F87XA
2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.
The Special Function Registers can be classified into
two sets: core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral features section.
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on: Details
POR, BOR on page:
Bank 0
00h⁽³⁾ INDF
01h
02h⁽³⁾
TMR0
PCL
03h⁽³⁾
04h⁽³⁾
STATUS
FSR
05h
PORTA
06h
PORTB
07h
08h⁽⁴⁾
09h⁽⁴⁾
0Ah^(1,3)
0Bh⁽³⁾
PORTC
PORTD
PORTE
PCLATH
INTCON
0Ch
PIR1
0Dh
PIR2
0Eh
TMR1L
0Fh
TMR1H
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 31, 150
Timer0 Module Register
xxxx xxxx 55, 150
Program Counter (PC) Least Significant Byte
0000 0000 30, 150
IRP
RP1
RP0
TO
PD
Z
DC
C 0001 1xxx 22, 150
Indirect Data Memory Address Pointer
xxxx xxxx 31, 150
—
— PORTA Data Latch when written: PORTA pins when read
--0x 0000 43, 150
PORTB Data Latch when written: PORTB pins when read
xxxx xxxx 45, 150
PORTC Data Latch when written: PORTC pins when read
xxxx xxxx 47, 150
PORTD Data Latch when written: PORTD pins when read
xxxx xxxx 48, 150
—
—
—
—
—
RE2
RE1
RE0 ---- -xxx 49, 150
—
—
— Write Buffer for the upper 5 bits of the Program Counter ---0 0000 30, 150
GIE
PSPIF⁽³⁾
PEIE
ADIF
TMR0IE
RCIF
INTE
TXIF
RBIE
SSPIF
TMR0IF
CCP1IF
INTF
RBIF 0000 000x 24, 150
TMR2IF TMR1IF 0000 0000 26, 150
—
CMIF
—
EEIF
BCLIF
—
—
CCP2IF -0-0 0--0 28, 150
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx 60, 150
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx 60, 150
10h
T1CON
—
— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 57, 150
11h
TMR2
Timer2 Module Register
0000 0000 62, 150
12h
T2CON
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 61, 150
13h
SSPBUF
Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx 79, 150
14h
SSPCON
WCOL SSPOV SSPEN
CKP
SSPM3
SSPM2
SSPM1 SSPM0 0000 0000 82, 82,
150
15h
CCPR1L
Capture/Compare/PWM Register 1 (LSB)
xxxx xxxx 63, 150
16h
CCPR1H
Capture/Compare/PWM Register 1 (MSB)
xxxx xxxx 63, 150
17h
CCP1CON
—
—
CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 64, 150
18h
RCSTA
SPEN
RX9
SREN CREN ADDEN FERR OERR RX9D 0000 000x 112, 150
19h
TXREG
USART Transmit Data Register
0000 0000 118, 150
1Ah
RCREG
USART Receive Data Register
0000 0000 118, 150
1Bh
CCPR2L
Capture/Compare/PWM Register 2 (LSB)
xxxx xxxx 63, 150
1Ch
CCPR2H
Capture/Compare/PWM Register 2 (MSB)
xxxx xxxx 63, 150
1Dh
CCP2CON
—
—
CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 64, 150
1Eh
ADRESH
A/D Result Register High Byte
xxxx xxxx 133, 150
1Fh
ADCON0
ADCS1 ADCS0 CHS2
CHS1
CHS0 GO/DONE —
ADON 0000 00-0 127, 150
Legend:
Note 1:
2:
3:
4:
5:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose
contents are transferred to the upper byte of the program counter.
Bits PSPIE and PSPIF are reserved on PIC16F873A/876A devices; always maintain these bits clear.
These registers can be addressed from any bank.
PORTD, PORTE, TRISD and TRISE are not implemented on PIC16F873A/876A devices, read as ‘0’.
Bit 4 of EEADRH implemented only on the PIC16F876A/877A devices.
 2003 Microchip Technology Inc.
DS39582B-page 19