PIC16LF877A-I Datasheet, PDF (155/234 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers

PIC16F87XA
14.11 Interrupts
The PIC16F87XA family has up to 15 sources of
interrupt. The Interrupt Control register (INTCON)
records individual interrupt requests in flag bits. It also
has individual and global interrupt enable bits.
Note:
Individual interrupt flag bits are set regard-
less of the status of their corresponding
mask bit or the GIE bit.
A global interrupt enable bit, GIE (INTCON<7>),
enables (if set) all unmasked interrupts or disables (if
cleared) all interrupts. When bit GIE is enabled and an
interrupt’s flag bit and mask bit are set, the interrupt will
vector immediately. Individual interrupts can be
disabled through their corresponding enable bits in
various registers. Individual interrupt bits are set
regardless of the status of the GIE bit. The GIE bit is
cleared on Reset.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit, which
re-enables interrupts.
The RB0/INT pin interrupt, the RB port change interrupt
and the TMR0 overflow interrupt flags are contained in
the INTCON register.
The peripheral interrupt flags are contained in the
Special Function Registers, PIR1 and PIR2. The
corresponding interrupt enable bits are contained in
Special Function Registers, PIE1 and PIE2, and the
peripheral interrupt enable bit is contained in Special
Function Register, INTCON.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack and the PC is loaded
with 0004h. Once in the Interrupt Service Routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs. The latency
is the same for one or two-cycle instructions. Individual
interrupt flag bits are set regardless of the status of their
corresponding mask bit, PEIE bit or GIE bit.
FIGURE 14-10: INTERRUPT LOGIC
EEIF
EEIE
PSPIF⁽¹⁾
PSPIE⁽¹⁾
BCLIF
BCLIE
CMIF
CMIE
ADIF
ADIE
RCIF
RCIE
TMR1IF
TMR1IE
CCP2IF
CCP2IE
TXIF
TXIE
SSPIF
SSPIE
CCP1IF
CCP1IE
TMR2IF
TMR2IE
TMR0IF
TMR0IE
INTF
INTE
RBIF
RBIE
PEIE
GIE
Note 1: PSP interrupt is implemented only on PIC16F874A/877A devices.
Wake-up (If in Sleep mode)
Interrupt to CPU
 2003 Microchip Technology Inc.
DS39582B-page 153