PIC16F882 Datasheet, PDF (28/288 Pages) Microchip Technology – 28/40/44-Pin, Enhanced Flash-Based 8-Bit CMOS Microcontrollers with nanoWatt Technology

PIC16F882/883/884/886/887
TABLE 2-1: PIC16F882/883/884/886/887 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0
Addr Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Page
Bank 0
00h INDF
Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 37,213
01h TMR0
Timer0 Module Register
xxxx xxxx 73,213
02h PCL
Program Counter’s (PC) Least Significant Byte
0000 0000 37,213
03h STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx 29,213
04h FSR
Indirect Data Memory Address Pointer
05h PORTA⁽³⁾
RA7
RA6
RA5
RA4
06h PORTB⁽³⁾
RB7
RB6
RB5
RB4
07h PORTC⁽³⁾
RC7
RC6
RC5
RC4
08h PORTD^(3,4)
RD7
RD6
RD5
RD4
09h PORTE⁽³⁾
—
—
—
—
RA3
RB3
RC3
RD3
RE3
RA2
RB2
RC2
RD2
RE2⁽⁴⁾
RA1
RB1
RC1
RD1
RE1⁽⁴⁾
RA0
RB0
RC0
RD0
RE0⁽⁴⁾
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
---- xxxx
37,213
39,213
48,213
53,213
57,213
59,213
0Ah PCLATH
0Bh INTCON
—
—
—
Write Buffer for upper 5 bits of Program Counter
---0 0000 37,213
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF⁽¹⁾ 0000 000x 31,213
0Ch PIR1
—
ADIF
RCIF
TXIF
SSPIF CCP1IF TMR2IF TMR1IF -000 0000 34,213
0Dh PIR2
OSFIF
C2IF
C1IF
EEIF
BCLIF ULPWUIF
—
CCP2IF 0000 00-0 35,213
0Eh TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx 76,213
0Fh TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx 76,213
10h T1CON
T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 79,213
11h TMR2
Timer2 Module Register
0000 0000 81,213
12h T2CON
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 82,213
13h SSPBUF
Synchronous Serial Port Receive Buffer/Transmit Register
14h SSPCON⁽²⁾
WCOL SSPOV SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
xxxx xxxx
0000 0000
179,213
177,213
15h CCPR1L
Capture/Compare/PWM Register 1 Low Byte (LSB)
xxxx xxxx 126,213
16h CCPR1H
Capture/Compare/PWM Register 1 High Byte (MSB)
xxxx xxxx 126,213
17h CCP1CON
P1M1
P1M0
DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 124,213
18h RCSTA
SPEN
RX9
SREN
CREN ADDEN FERR
OERR
RX9D 0000 000x 159,213
19h TXREG
EUSART Transmit Data Register
0000 0000 151,213
1Ah RCREG
EUSART Receive Data Register
0000 0000 156,213
1Bh CCPR2L
Capture/Compare/PWM Register 2 Low Byte (LSB)
xxxx xxxx 126,213
1Ch ^CCPR2H
Capture/Compare/PWM Register 2 High Byte (MSB)
xxxx xxxx _126,214
1Dh CCP2CON
—
—
DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 125,214
1Eh ADRESH
A/D Result Register High Byte
xxxx xxxx 99,214
1Fh ADCON0
ADCS1 ADCS0
CHS3
CHS2
CHS1
CHS0 GO/DONE ADON 0000 0000 104,214
Legend:
Note 1:
2:
3:
4:
– = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
MCLR and WDT Reset do not affect the previous value data latch. The RBIF bit will be cleared upon Reset but will set again if the
mismatch exists.
When SSPCON register bits SSPM<3:0> = 1001, any reads or writes to the SSPADD SFR address are accessed through the SSPMSK
register. See Registers • and 13-4 for more detail.
Port pins with analog functions controlled by the ANSEL and ANSELH registers will read ‘0’ immediately after a Reset even though the
data latches are either undefined (POR) or unchanged (other Resets).
PIC16F884/PIC16F887 only.
DS41291D-page 26
Preliminary
© 2007 Microchip Technology Inc.