PIC16F882 Datasheet, PDF (279/288 Pages) Microchip Technology – 28/40/44-Pin, Enhanced Flash-Based 8-Bit CMOS Microcontrollers with nanoWatt Technology

PIC16F882/883/884/886/887
Associated Registers
Baud Rate Generator........................................ 161
Asynchronous Mode ................................................. 151
12-bit Break Transmit and Receive .................. 167
Associated Registers
Receive..................................................... 157
Transmit.................................................... 153
Auto-Wake-up on Break ................................... 166
Baud Rate Generator (BRG) ............................ 161
Clock Accuracy ................................................. 158
Receiver............................................................ 154
Setting up 9-bit Mode with Address Detect....... 156
Transmitter........................................................ 151
Baud Rate Generator (BRG)
Auto Baud Rate Detect ..................................... 165
Baud Rate Error, Calculating ............................ 161
Baud Rates, Asynchronous Modes .................. 162
Formulas ........................................................... 161
High Baud Rate Select (BRGH Bit) .................. 161
Synchronous Master Mode ............................... 169, 173
Associated Registers
Receive..................................................... 172
Transmit.................................................... 170
Reception.......................................................... 171
Transmission .................................................... 169
Synchronous Slave Mode
Associated Registers
Receive..................................................... 174
Transmit.................................................... 173
Reception.......................................................... 174
Transmission .................................................... 173
F
Fail-Safe Clock Monitor....................................................... 71
Fail-Safe Condition Clearing ....................................... 71
Fail-Safe Detection ..................................................... 71
Fail-Safe Operation..................................................... 71
Reset or Wake-up from Sleep..................................... 71
Firmware Instructions........................................................ 225
Flash Program Memory .................................................... 111
Writing....................................................................... 117
Fuses. See Configuration Bits
G
General Call Address Support .......................................... 188
General Purpose Register File............................................ 22
I
I²C (MSSP Module)
ACK Pulse......................................................... 185, 186
Addressing ................................................................ 186
Read/Write Bit Information (R/W Bit) ........................ 186
Reception.................................................................. 186
Serial Clock (RC3/SCK/SCL).................................... 186
Slave Mode ............................................................... 185
Transmission............................................................. 186
I²C Master Mode Reception.............................................. 194
I²C Master Mode Repeated Start Condition Timing.......... 193
I²C Module
Acknowledge Sequence Timing................................ 197
Baud Rate Generator................................................ 191
BRG Block Diagram.................................................. 191
BRG Reset Due to SDA Arbitration During
Start Condition .................................................. 201
BRG Timing .............................................................. 191
Bus Collision
Acknowledge .................................................... 199
Repeated Start Condition ................................. 202
Repeated Start Condition Timing (Case1)........ 202
Repeated Start Condition Timing (Case2)........ 202
Start Condition.................................................. 200
Start Condition Timing .............................. 200, 201
Stop Condition .................................................. 203
Stop Condition Timing (Case 1) ....................... 203
Stop Condition Timing (Case 2) ....................... 203
Bus Collision timing .................................................. 199
Clock Arbitration ....................................................... 198
Clock Arbitration Timing (Master Transmit) .............. 198
Effect of a Reset ....................................................... 198
General Call Address Support .................................. 188
Master Mode............................................................. 189
Master Mode 7-bit Reception Timing........................ 196
Master Mode Operation............................................ 190
Master Mode Start Condition Timing ........................ 192
Master Mode Support ............................................... 189
Master Mode Transmission ...................................... 194
Master Mode Transmit Sequence ............................ 190
Multi-Master Mode.................................................... 199
Repeat Start Condition Timing Waveform ................ 193
Sleep Operation........................................................ 198
Stop Condition Receive or Transmit Timing ............. 198
Stop Condition Timing .............................................. 197
Waveforms for 7-bit Reception ................................. 187
Waveforms for 7-bit Transmission............................ 187
ID Locations...................................................................... 223
In-Circuit Debugger........................................................... 224
In-Circuit Serial Programming (ICSP)............................... 223
Indirect Addressing, INDF and FSR registers..................... 37
Instruction Format............................................................. 225
Instruction Set................................................................... 225
ADDLW..................................................................... 227
ADDWF .................................................................... 227
ANDLW..................................................................... 227
ANDWF .................................................................... 227
BCF .......................................................................... 227
BSF........................................................................... 227
BTFSC...................................................................... 227
BTFSS ...................................................................... 228
CALL......................................................................... 228
CLRF ........................................................................ 228
CLRW ....................................................................... 228
CLRWDT .................................................................. 228
COMF ....................................................................... 228
DECF........................................................................ 228
DECFSZ ................................................................... 229
GOTO ....................................................................... 229
INCF ......................................................................... 229
INCFSZ..................................................................... 229
IORLW ...................................................................... 229
IORWF...................................................................... 229
MOVF ....................................................................... 230
MOVLW .................................................................... 230
MOVWF.................................................................... 230
NOP.......................................................................... 230
RETFIE..................................................................... 231
RETLW ..................................................................... 231
RETURN................................................................... 231
RLF........................................................................... 232
RRF .......................................................................... 232
SLEEP ...................................................................... 232
SUBLW..................................................................... 232
© 2007 Microchip Technology Inc.
Preliminary
DS41291D-page 277