KSZ8463ML Datasheet, PDF (230/259 Pages) Micrel Semiconductor – IEEE 1588 Precision Time Protocol-Enabled, Three-Port, 10/100-Managed Switch with MII or RMII

Micrel, Inc.
KSZ8463ML/RL/FML/FRL
PHY1 (PHYAD = 0x1) and PHY2 (PHYAD = 0x2): Register 1 (REGAD = 0x1) -> MII Basic Status (Continued)
Bit Default R/W Description
Auto-Negotiation Capable
3
1
RO 1 = Auto-negotiation capable.
0 = Not auto-negotiation capable.
Link Status
2
0
RO 1 = Link is up.
0 = Link is down.
Jabber Test
1
0
RO
Not supported.
Extended Capable
0
0
RO 1 = Extended register capable.
0 = Not extended register capable.
PHY1 (PHYAD = 0x1) and PHY2 (PHYAD = 0x2): Register 2 (REGAD = 0x2) -> PHYID High
Bit Default R/W Description
15 − 0 0x0022 RO PHY ID High Word
PHY1 (PHYAD = 0x1) and PHY2 (PHYAD = 0x2): Register 3 (REGAD = 0x3) -> PHYID Low
Bit Default R/W Description
15 − 0 0x1430 RO PHY ID Low Word
PHY1 (PHYAD = 0x1) and PHY2 (PHYAD = 0x2): Reg. 4 (REGAD = 0x4) -> Auto-Negotiation Advertisement Ability
Bit
Default R/W Description
Next Page
15
0
RO _{Not supported.}
14
0
RO Reserved
Remote Fault
13
0
RO
Not supported.
12 − 11
0x0
RO Reserved
Pause (Flow Control Capability)
10
1
RW 1 = Advertise pause ability.
0 = Do not advertise pause capability.
9
0
RW Reserved
Advertise 100BT Full-Duplex
8
1
RW 1 = Advertise 100BT full-duplex capable.
0 = Do not advertise 100BT full-duplex capability.
Advertise 100BT Half-Duplex
7
1
RW 1= Advertise 100BT half-duplex capable.
0 = Do not advertise 100BT half-duplex capability.
June 11, 2014
230
Revision 1.0