KSZ8441HL Datasheet, PDF (167/194 Pages) Micrel Semiconductor – IEEE 1588v2, Precision Time Protocol-Enabled, 10/100Mbs, Ethernet End-Point Connection with 8- or 16-Bit Host Bus Interface

Micrel, Inc.
Bit
Default
3
0
2
1
1
0
0
0
KSZ8441HL/FHL
R/W
Description
RO
Reserved
Enable the IPv4/UDP Checksum Calculation for Egress Packets
1 = The device will re-calculate and generate a 2-byte checksum value due to a frame
contents change.
RW
0 = The checksum field is set to zero.
If the IPv4/UDP checksum is zero, the checksum will remain zero regardless of this bit
setting.
For IPv6/UDP, the checksum is always updated.
Announce Message from Port 1
RW
1 = The Announce message is received from Port 1 direction.
0 = The Announce message is not received from Port 1 direction.
RW
Reserved
PTP Domain and Version Register (0x624 – 0x625): PTP_DOMAIN_VER
This register contains the PTP Domain and Version Information.
Bit
Default
R/W
Description
15-12
0x0
RO
Reserved
11-8
0x2
7-0
0x00
PTP Version
This is the value of PTP message version number field. All PTP packets will be captured
RW
when the receive PTP message version matches the value in this field.
All PTP packets will be dropped if the receive PTP message version does not match the
value in this field.
PTP Domain
This is the value of PTP message domain number field. If the DOMAIN_EN bit is set to “1”,
RW
the PTP messages will be filtered out and only forwarded to the Host Port if the domain
number matches.
If the DOMAIN_EN bit is set to “0”, the domain number field will be ignored under certain
circumstances.
0x626 – 0x63F: Reserved
PTP Port 1 Receive Latency Register (0x640 – 0x641): PTP_P1_RX_LATENCY
This register contains the PTP Port 1 receive latency value in nanoseconds.
Bit
Default
R/W
Description
15-0
0x019F
PTP Port 1 RX Latency in Nanoseconds [15:0]
RW
This register is used to set the fixed receive delay value from Port 1 wire to RX timestamp
reference point. The default value is 415ns.
June 17, 2014
167
Revision 1.0