KSZ8441HL Datasheet, PDF (148/194 Pages) Micrel Semiconductor – IEEE 1588v2, Precision Time Protocol-Enabled, 10/100Mbs, Ethernet End-Point Connection with 8- or 16-Bit Host Bus Interface

Micrel, Inc.
KSZ8441HL/FHL
Trigger Output Unit 1 Configuration and Control Register 1 (0x228 – 0x229):
TRIG1_CFG_1
This register (1 of 8) contains the Trigger Output Unit 1 configuration and control bits.
Bit
Default
R/W
Description
15
0
Enable This Trigger Output Unit in Cascade Mode
RW
1 = Enable this Trigger Output Unit in cascade mode.
0 = Disable this Trigger Output Unit in cascade mode.
14
0
Indicate a Tail Unit for This Trigger Output Unit in Cascade Mode
1 = This Trigger Output Unit is the last unit of the chain in cascade mode.
0 = This Trigger Output Unit is not the last unit of a chain in cascade mode.
RW
Note: When this bit is set “0” in all CFG_1 Trigger Units, and all units are in
cascade mode, the iteration count is ignored and it becomes infinite. To stop
the infinite loop, set the respective bit[11:0] in TRIG_SW_RST register.
13-10
0xF
Select Upstream Trigger Unit in Cascade Mode
These bits select one of the 12 upstream trigger output units in cascade mode.
Note that 0x0 indicates TOU1, and 0xB indicates TOU12. (Values 0xC to 0xF do not
RW
indicate any TOU.) For example, if units 1, 2 and 3 (tail unit) are set up in cascade mode,
then these 4 bits are set as follows at the three trigger output units: Unit 1 is set to 0x2
(indicates TOU3), at unit 2 is set to 0x0 (indicates TOU1) and at unit 3 is to set 0x1
(indicates TOU2).
9
0
Trigger Now
1 = Immediately create the trigger output if the trigger target time is less than
RW
the system time clock.
0 = Wait for the trigger target time to occur to trigger the event output.
8
0
Trigger Notify
1 = Enable reporting both TRIG_DONE and TRIG_ERR status as well as
RW
interrupt to host if the interrupt enable bit is set in the TRIG_IE register.
0 = Disable reporting both TRIG_DONE and TRIG_ERR status.
7
0
RO
Reserved
6-4
000
Trigger Output Signal Pattern
This field selects the trigger output signal pattern when TRIG_EN = “1” and trigger target
time has reached the system time:
000: TRIG_NEG_EDGE - Generates negative edge (from default “H” -> “L” and stays “L”).
001: TRIG_POS_EDGE - Generates positive edge (from default “L” -> “H” and stays “H”).
010: TRIG_NEG_PULSE - Generates negative pulse (from default “H” -> “L” pulse-> “H”
and stays “H”). The pulse width is defined in TRIG1_CFG_2 register.
011: TRIG_POS_PULSE - Generates positive pulse (from default “L” -> “H” pulse -> “L”
and stays “L)”. The pulse width is defined in TRIG1_CFG_2 register.
100: TRIG_NEG_CYCLE - Generates negative periodic signal. The “L” pulse width is
defined in TRIG1_CFG_2 register, the cycle width is defined in TRIG1_CFG_3/4 registers
RW
and the number of cycles is defined in TRIG1_CFG_5 register (it is an infinite number if
this register value is zero).
101: TRIG_POS_CYCLE - Generates positive periodic signal. The “H” pulse width is
defined in TRIG1_CFG_2 register, the cycle width is defined in TRIG1_CFG_3/4 registers
and the number of cycles is defined in TRIG1_CFG_5 register (it is an infinite number if
this register value is zero).
110: TRIG_REG_OUTPUT - Generates an output signal from a 16-bit register. This 16-bit
register bit-pattern in TRIG1_CFG_6 is shifted LSB bit first and looped, each bit width is
defined in TRIG1_CFG_3/4 registers and total number of bits to shift out is defined in
TRIG1_CFG_5 register (it is an infinite number if this register value is zero).
111: Reserved
Note: the maximum output clock frequency is up to 12.5MHz.
June 17, 2014
148
Revision 1.0