KSZ8441HL Datasheet, PDF (119/194 Pages) Micrel Semiconductor – IEEE 1588v2, Precision Time Protocol-Enabled, 10/100Mbs, Ethernet End-Point Connection with 8- or 16-Bit Host Bus Interface

Micrel, Inc.
KSZ8441HL/FHL
Port 1 EEE Wake Error Count Register (0x0E2 – 0x0E3): P1EEEWEC
This register contains the Port 1 EEE wake error count information. Note that EEE is not supported in Fiber Mode.
Bit
Default Value
R/W Description
15-0
0x0000
Port 1 EEE Wake Error Count
This counter is incremented by each transition of lpi_wake_timer_done from FALSE to
RW TRUE. It means the wake-up time is longer than 20.5μs.
The value will be held at all ones in the case of overflow and will be cleared to zero after
this register is read.
Port 1 EEE Control/Status and Auto-Negotiation Expansion Register (0x0E4 – 0x0E5):
P1EEECS
This register contains the Port 1 EEE control/status and auto-negotiation expansion information. Note that EEE is not supported in Fiber
Mode.
Bit
Default
R/W
Description
15
1
RW
Reserved
14
0
Hardware 100BT EEE Enable Status
RO
1 = 100BT EEE is enabled by hardware based NP exchange.
0 = 100BT EEE is disabled.
TX LPI Received
1 = Indicates that the transmit PCS has received low power idle (LPI) signaling
RO/LH
one or more times since the register was last read.
13
0
(Latching
High)
0 = Indicates that the PCS has not received low power idle (LPI) signaling.
The status will be latched high and stay that way until cleared. To clear this status bit, a “1”
needs to be written to this register bit.
12
0
TX LPI Indication
1 = Indicates that the transmit PCS is currently receiving low power idle (LPI)
RO
signals.
0 = Indicates that the PCS is not currently receiving low power idle (LPI) signals.
This bit will dynamically indicate the presence of the TX LPI signal.
RX LPI Received
1 = Indicates that the receive PCS has received low power idle (LPI) signaling one
RO/LH
11
0
(Latching
or more times since the register was last read.
High)
0 = Indicates that the PCS has not received low power idle (LPI) signaling.
The status will be latched high and stay that way until cleared. To clear this status bit, a “1”
needs to be written to this register bit.
10
0
RX LPI Indication
1 = Indicates that the receive PCS is currently receiving low power idle (LPI)
RO
signals.
0 = Indicates that the PCS is not currently receiving low power idle (LPI) signals.
This bit will dynamically indicate the presence of the RX LPI signal.
9-8
00
RW
Reserved
7
0
RO
Reserved
6
1
Received Next Page Location Able
RO
1 = Received Next Page storage location is specified by bit [6:5].
0 = Received Next Page storage location is not specified by bit [6:5].
5
1
Received Next Page Storage Location
RO
1 = Link partner Next Pages are stored in P1ALPRNP (Reg. 0x0DE – 0x0DF).
0 = Link partner Next Pages are stored in P1ANLPR (Reg. 0x056 – 0x057).
June 17, 2014
119
Revision 1.0