7025E Datasheet, PDF (6/20 Pages) Maxwell Technologies – (8K x 16-Bit) Dual Port RAM High-Speed CMOS

(8K x 16-Bit) Dual Port RAM High-Speed CMOS
7025E
TABLE 9. 7025E AC ELECTRICAL CHARACTERISTICS FOR WRITE MASTER/SLAVE CONFIGURATION
(V_CC = 5V ± 10%, V_SS = 0V, T_A = -55 TO 125 ^°C)
PARAMETER
SYMBOL
MIN
MAX
UNIT
For Master Only
BUSY Access Time to Address Match
-35
-45
t_BAA
ns
--
35
--
35
BUSY Disable Time to Address Not Matched
-35
-45
t_BDA
ns
--
30
--
30
BUSY Access Time to Chip Select Low
-35
-45
t_BAC
ns
--
30
--
30
BUSY Disable Time to Chip Select High
-35
-45
Write Pulse to Data Delay ¹
-35
-45
Write Data Valid to Read Data Delay ¹
-35
-45
Arbitration Priority Setup Time ²
-35
-45
t_BDC
ns
--
25
--
25
t_WDD
ns
--
60
--
70
t_DDD
ns
--
45
--
55
t_APS
5
5
ns
--
--
BUSY Disable to Valid Data
-35
-45
For Slave Only
Write to BUSY Input ⁴
Write Hold after BUSY ⁵
Write Pulse to Data Delay ¹
-35
-45
Write Data Valid to Read Data Delay ¹
-35
-45
t_BDD
ns
--
3
--
3
t_WB
0
--
ns
t_WH
25
--
ns
t_WDD
ns
--
60
--
70
t_DDD
ns
--
45
--
55
1. Port to port timing delay through RAM cells from writing port to reading port.
2. To ensure that the earlier of the two ports wins.
3. t_BDD is a calculated parameter and is the greater of 0, t_WDD - t_WP (actual) or t_DDD - t_WD (actual).
4. To ensure that the write cycle is inhibited during contention.
5. To ensure that a write cycle is completed after contention.
08.15.02 Rev 2
All data sheets are subject to change without notice 6
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