7025E Datasheet, PDF (10/20 Pages) Maxwell Technologies – (8K x 16-Bit) Dual Port RAM High-Speed CMOS

(8K x 16-Bit) Dual Port RAM High-Speed CMOS
7025E
FIGURE 1. TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE1,2,3
FIGURE 2. TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE1,4,5
1. F/W is high for read cycles.
2. Device is continuously enabled, CS = V_IL, UB or LB = V_L. This waveform cannot be used for semaphore reads.
3. CE = V_IL.
4. Addresses valid prior to or coincident with CS transition.
5. To access RAM, CS = V_L, UB or LB = V_IL, SEM = V_IH. To access semaphore, CS = V_IH, SEM = V_IL.
08.15.02 Rev 2
All data sheets are subject to change without notice 10
©2002 Maxwell Technologies
All rights reserved.