7025E Datasheet, PDF (15/20 Pages) Maxwell Technologies – (8K x 16-Bit) Dual Port RAM High-Speed CMOS

(8K x 16-Bit) Dual Port RAM High-Speed CMOS
RIGHT ADDRESS VALID FIRST
7025E
1. CS_L = CS_R = V_IL.
FIGURE 11. WAVEFORM OF INTERRUPT TIMING ¹
SET ADDRESS
CLEAR ADDRESS
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite
from “A”.
2. See interrupt truth table.
3. Timing depends on which enable signal is asserted last.
4. Timing depends on which enable signal is de-asserted first.
08.15.02 Rev 2
All data sheets are subject to change without notice 15
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