7025E Datasheet, PDF (17/20 Pages) Maxwell Technologies – (8K x 16-Bit) Dual Port RAM High-Speed CMOS

(8K x 16-Bit) Dual Port RAM High-Speed CMOS
FIGURE 14. TIMING WAVEFORM OF SEMAPHORE CONTENTION ^1,3,4
7025E
1. D_OR = D_OL = V_IL, CS_R = CS_L = V_IH, semaphore Flag is released from both sides (reads as ones from both sides) at
cycle start.
2. Either side “A” = left and side “B” = right, or side “A” = right and side “B” = left.
3. This parameter is measured from the point where R/W_A or SEM_A goes high until R/W_B or SEM_B goes high.
4. If t_SPS is violated, the semaphore will fall positively to one side or the other, but there is no guaranty which side will
obtain the flag.
08.15.02 Rev 2
All data sheets are subject to change without notice 17
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