97SD3248 Datasheet, PDF(32/40 Page) Maxwell Technologies – 1.5Gb SDRAM 8-Meg X 48-Bit X 4-Banks

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97SD3248 Datasheet, PDF (32/40 Pages) Maxwell Technologies – 1.5Gb SDRAM 8-Meg X 48-Bit X 4-Banks

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1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM

97SD3248

Recharge command Interval (same bank): To stop output data

CAS Latency = 2, Burst Length = 1, 2, 4, 8

CAS Latency = 3, Burst Length = 1, 2, 4, 8

d to Precharge command interval (same bank): When the precharge command is executed for the same

bank as the write command that preceded it, the minimum interval between the two commands is 1 clock.

However, if the burst write operation is unfinished, the data must be masked by means of DQM for

assurance of the clock defined by tDPL.

WRITE to PRECHARGE Command Interval (same bank)

Burst Length = 4 (To stop write operation)

02.04.05 Rev 3

All data sheets are subject to change without notice 32

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