97SD3248 Datasheet, PDF (20/40 Pages) Maxwell Technologies – 1.5Gb SDRAM 8-Meg X 48-Bit X 4-Banks

1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM
97SD3248
Operation of the SDRAM
The following section shows operation examples of 97SD32488.
Note: The SDRAM should be used according to the product capability ( See Pin Description and AC
Characteristics.)
Read/Write Operations:
Bank Active: Before executing a read or write operation, the corresponding bank and the row address must
be activated by the bank active (ACTV) command. An interval of t_RCD is required between the bank active
command input and the following read/write command input.
Read operation: A read operation starts when a read command is input. The output buffer becomes Low-Z
in the (CAS latency - 1) cycle after read command set. The SDRAM can perform a burst read operation.
The burst length can be set to 1, 2, 4, or 8. The start address for a burst read is specified by the column
address and the bank select address (BA0/BA1) at the read command set cycle. In a read operation, data
output starts after the number of clocks specified by the CAS latency. The CAS latency can be set to 2 or 3.
When the burst length is 1, 2, 4, or 8, the D_OUT buffer automatically becomes High-Z at the next clock after
the successive burst-length data has been output.
The CAS latency and burst length must be specified at the mode register.
02.04.05 Rev 3
All data sheets are subject to change without notice 20
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