97SD3248 Datasheet, PDF (14/40 Pages) Maxwell Technologies – 1.5Gb SDRAM 8-Meg X 48-Bit X 4-Banks

1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM
97SD3248
CURRENT STATE
CS RAS CAS WE
ADDRESS
COMMAND
OPERATION
Write with auto- H
x
x
x
x
precharge
DESL
Continue burst to end and pre-
charge
L
H
H
H
x
NOP
Continue burst to end and pre-
charge
L
H
L
H
BA, CA, A10 READ/READ A
ILLEGAL¹
L
H
L
L
BA, CA, A10 WRIT/WRIT A
ILLEGAL¹
L
L
H
H
BA, RA
ACTV
Other bank active
ILLEGAL on same bank⁴
L
L
H
L
BA, A10
PRE, PALL
ILLEGAL¹
L
L
L
H
x
REF, SELF
ILLEGAL
L
L
L
L
MODE
MRS
ILLEGAL
Refresh ( auto- H
x
x
x
x
refresh)
L
H
H
H
x
DESL
NOP
L
H
L
H
BA, CA, A10 READ/READ A
Enter IDLE after t_RC
Enter IDLE after t_RC
ILLEGAL³
L
H
L
L
BA, CA, A10 WRIT/WRIT A
ILLEGAL³
L
L
H
H
BA, RA
ACTV
ILLEGAL³
L
L
H
L
BA, A10
PRE, PALL
ILLEGAL³
L
L
L
H
x
REF, SELF
ILLEGAL
L
L
L
L
MODE
MRS
1. Illegal for same bank, except for another bank
2. NOP for same bank, except for another bank
3. Illegal for all banks
4. If t_RRD is not satisfied, this operation is illegal
5. An interval of t_DPL is required between the final valid data input and the precharge command
ILLEGAL
From PRECHARGE state, command operation
To [DESL], [NOP]: When these commands
elapsed from the completion of precharge.
are
executed,
the
SDRAM
enters
the
IDLE
state
after
t_RP
has
From IDLE state, command operation
To [DESL], [NOP], [PRE], or [PALL]: These commands result in no operation.
To [ACTV]: The bank specified by the address pins and the ROW address is activated.
To [REF], [SELF]: The SDRAM enters refresh mode (auto-refresh or self-refresh).
To [MRS]: The synchronous DRAM enters the mode register set cycle.
From ROW ACTIVE state, command operation
To [DESL], [NOP]: These commands result in no operation.
To [READ], [READ A]: A read operation starts. (However, an interval of t_RCD is required.)
To [WRIT], [WRIT A]: A write operation starts. (However, an interval of t_RCD is required.)
02.04.05 Rev 3
All data sheets are subject to change without notice 14
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