97SD3248 Datasheet, PDF (22/40 Pages) Maxwell Technologies – 1.5Gb SDRAM 8-Meg X 48-Bit X 4-Banks

1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM
97SD3248
Write Operation: Burst write or single write mode is selected by the OPCODE (BA1, BA0, A12, A11, A10,
A9, A8) of the mode register.
1. Burst write: A burst write operation is enabled by setting OPCODE (A9, A8) to (0, 0). A burst write starts
in the same clock as a write command set. (The latency of data input is 0 clock.) The burst length can be set
to 1, 2, 4, or 8, like burst read operations. The write start address is specified by the column address and the
bank select address (BA0/BA1) at the write command set cycle.
2. Single write: A single write operation is enabled by setting OPCODE ( A9, A8) to (1, 0). In a single write
operation, data is only written to the column address and the bank select address (BA0/BA1) specified by
the write command set cycle without regard to the burst length setting. ( The latency of data input is 0 clock.)
02.04.05 Rev 3
All data sheets are subject to change without notice 22
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