DS80C400_07 Datasheet, PDF(90/97 Page) Maxim Integrated Products

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DS80C400_07 Datasheet, PDF (90/97 Pages) Maxim Integrated Products – Network Microcontroller

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DS80C400 Network Microcontroller

Table 28. Interrupt Summary

NAME

PFI

INT0

FUNCTION

Power-Fail Interrupt

External Interrupt 0

VECTOR

33h

03h

TF0

Timer 0

0Bh

INT1

External Interrupt 1

13h

TF1

Timer 1

1Bh

TI0 or RI0

Serial Port 0

23h

TF2

Timer 2

2Bh

TI1 or RI1

Serial Port 1

3Bh

INT2

INT3

INT4

External Interrupts 2â5,

1-Wire Bus Master,

43h

Interrupt

INT5/OWMI

TF3

Timer 3

4Bh

TI2 or RI2

Serial Port 2

53h

WPI

Write Protect Interrupt 5Bh

C0I

CAN0 Interrupt

6Bh

EAI

Ethernet Activity

73h

WDTI

Watchdog Timer

63h

EPMI

Ethernet Power Mode 7Bh

NATURAL

PRIORITY

FLAG BIT

PFI (WDCON.4)

IE0 (TCON.1)

(Note 2)

TF0 (TCON.5)

(Note 1)

IE1 (TCON.3)

(Note 2)

TF1 (TCON.7)

(Note 1)

RI_0(SCON0.0)

TI_0(SCON0.1)

TF2(T2CON.7)

RI_1(SCON1.0)

TI_1(SCON1.1)

IE2 (EXIF.4)

IE3 (EXIF.5)

IE4 (EXIF.6)

IE5 (EXIF.7)

(Note 3)

TF3 (T3CM.7))

IE4 (EXIF.6)

WPIF (MCON2.7)

Various

TIF (BCUC.5)

RIF (BCUC.4)

WDIF (WDCON.3)

EPMF (BCUC.6)

ENABLE BIT

EPFI (WDCON.5)

EX0 (IE.0)

ET0 (IE.1)

EX1 (IE.2)

ET1 (IE.3)

ES0 (IE.4)

ET2 (IE.5)

ES1 (IE.6)

EX2-5 (EIE.0)

EOWMI (Note 3)

ET3 (EIE.1)

ES2 (EIE.2)

EWPI (EIE.3)

C0IE (EIE.6)

EAIE (EIE.5)

EWDI (EIE.4)

EPMIE (EIE.7)

PRIORITY

CONTROL BIT

N/A

PX0 (IP.0)

PT0 (IP.1)

PX1 (IP.2)

PT1 (IP.3)

PS0 (IP.4)

PT2 (IP.5)

PS1 (IP.6)

PX2-5 (EIP.0)

PT3 (EIP.1)

PS2 (EIP.2)

PWPI (EIP.3)

C0IP (EIP.6)

EAIP (EIP.5)

PWDI (EIP.4)

EPMIP (EIP.7)

Unless marked, all flags must be cleared by the application software.

Note 1: Cleared automatically by hardware when the service routine is entered.

Note 2: If edge-triggered, the flag is cleared automatically by hardware when the service routine is entered. If level-triggered, the flag follows the

state of the interrupt pin.

Note 3: The global 1-Wire interrupt-enable bit (EOWMI) and individual 1-Wire interrupt source enables are located in the internal 1-Wire bus

master interrupt enable register, and must be accessed through the OWMAD and OWMDR SFRs. Individual 1-Wire interrupt source

flag bits that are located in the internal 1-Wire bus master Interrupt flag register are accessed in the same way.

Oneâs Complement Adder

The DS80C400 implements a oneâs complement adder to support the Internet checksum algorithm. The adder

contains a 16-bit accumulator and is accessed through the oneâs complement adder data (OCAD) SFR.

Writing two bytes to the OCAD register initiates a summation between the 16-bit accumulator and the 16-bit value

entered. When entering a new 16-bit value for summation, the MSB should be loaded first and the LSB loaded

second. The calculation begins on the first machine cycle following the second write to the OCAD register and

executes in a single machine cycle. This allows back-to-back writes of 16-bit data to the OCAD register for

summation. The carry out bit from the high-order bit of the calculation is added back into the low-order bit of the

accumulator.

Reading two bytes from the OCAD register downloads the contents of the 16-bit accumulator. When reading the

16-bit accumulator through the OCAD register, the MSB is unloaded first and the LSB is unloaded second. The 16-

bit accumulator is cleared to 0000h following the second read of the OCAD SFR.

The following is an example sequence for producing an Internet checksum for transmission.

â¢ Read OCAD twice to make certain that the 16-bit accumulator = 0000h

â¢ Write MSB of 16-bit value to OCAD

â¢ Write LSB of 16-bit value to OCAD

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