DS80C400_07 Datasheet, PDF (40/97 Pages) Maxim Integrated Products – Network Microcontroller

DS80C400 Network Microcontroller
TIMED-ACCESS PROTECTION
Selected SFR bits are critical to operation, making it desirable to protect them against an accidental write
operation. The timed-access procedure prevents errant behavior from accidentally altering bits that would seriously
affect microcontroller operation. The timed-access procedure requires that the write of a protected bit be
immediately preceded by the following two instructions:
MOV 0C7h, #0AAh
MOV 0C7h, #55h
Writing an AAh followed by a 55h to the timed access register (location C7h), opens a three-cycle window that
allows software to modify one of the protected bits. The protected bits are:
SFR
EXIF (91h)
P4CNT (92h)
ACON (9Dh)
—
—
—
—
P5CNT (A2h)
C0C (A3h)
P6CNT (B2h)
MCON (C6h)
—
—
COR (CEh)
—
—
—
MCON1 (D6h)
MCON2 (D7h)
WDCON (D8h)
—
—
—
EBS (E5h)
—
BIT(S)
EXIF.0
P4CNT.5–0
ACON.5
ACON.4
ACON.3
ACON.2
ACON.1–0
P5CNT.2–0
C0C.3
P6CNT.5–0
MCON.7–6
MCON.5
MCON.3–0
COR.7
COR.4–3
COR.2–1
COR.0
MCON1.3–0
MCON2.6–4
MCON2.3–0
WDCON.6
WDCON.3
WDCON.1
WDCON.0
EBS.7
EBS.4–0
NAME
BGS
—
MROM
BPME
BROM
SA
AM1–AM0
—
CRST
—
IDM1–IDM0
CAN
PDCE3–PDCE0
IRDACK
C0BPR7–C0BPR6
COD1–COD0
CLKOE
PDCE7–PDCE4
WPR2–WPR0
WPE3–WPE0
POR
WDIF
EWT
RWT
FPE
BS4-BS0
FUNCTION
Bandgap Select
Port 4 Pin Configuration Control Bits
Merge ROM
Breakpoint Mode Enable
By-Pass ROM
Stack Address Mode
Address Mode Select Bits
Port 5 Pin Configuration Control Bits
CAN 0 Reset
Port 6 Pin Configuration Control Bits
Internal Memory Configuration Bits
CMA Data Memory Assignment
Program/Data-Chip Enables
IRDA Clock-Output Enable
CAN 0 Baud Rate Prescale Bits
CAN Clock-Output Divide Bits
CAN Clock-Output Enable
Program/Data Chip Enable
Write-Protect Range Bits
Write-Protect Enable Bits
Power-On Reset Flag
Watchdog Interrupt Flag
Watchdog Reset Enable
Reset Watchdog Timer
Flush Filter Failed-Packet Enable
Buffer Size Configuration Bits
MEMORY ARCHITECTURE
The DS80C400 incorporates four internal memory areas:
• 256 Bytes of scratchpad (or direct) RAM
• 8kB of SRAM for Ethernet MAC transmit/receive buffer memory
• 1kB of SRAM configurable as various combinations of data memory and stack memory
• 256 Bytes of RAM reserved for the CAN message centers
• 64kB embedded ROM firmware
Up to 16MB of external code memory can be addressed through a multiplexed or demultiplexed 22-bit address
bus/8-bit data bus through eight available chip enables. Up to 4MB of external data memory can be accessed over
the same address/data buses through peripheral-enable signals. The DS80C400 also permits a 16MB merged
program/data memory map.
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