DS80C400_07 Datasheet, PDF (42/97 Pages) Maxim Integrated Products – Network Microcontroller

Table 3. Extended Address Generation
P4CNT.5–3
000
001
010
011
100
101
110 or 111 (default)
P6.5
I/O
I/O
I/O
I/O
I/O
I/O
A21
P6.4
I/O
I/O
I/O
I/O
I/O
A20
A20
P4.7
I/O
I/O
I/O
I/O
A19
A19
A19
P4.6
I/O
I/O
I/O
A18
A18
A18
A18
P4.5
I/O
I/O
A17
A17
A17
A17
A17
P4.4
I/O
A16
A16
A16
A16
A16
A16
DS80C400 Network Microcontroller
MAX MEMORY ACCESSIBLE
per CE
32kB (Note 1)
128kB
256kB
512kB
1MB
2MB (Note 2)
4MB (Note 3)
Table 4. Chip-Enable Generation
P6CNT.2–0
000 (default)
(Note 2)
100
101
110
111 (Note 2)
PORT 6 PIN FUNCTION
P6.3
P6.2
P6.1
P6.0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CE4
I/O
I/O
CE5
CE4
I/O
CE6
CE5
CE4
CE7
CE6
CE5
CE4
P4CNT.2–0
000
100
101
110
111 (default)
PORT 4 PIN FUNCTION
P4.3
P4.2
P4.1
P4.0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CE0
I/O
I/O
CE1
CE0
I/O
CE2
CE1
CE0
CE3
CE2
CE1
CE0
Note 1: Only 32kB of memory is accessible per chip enable for the P4CNT.5-3 = 000b setting, which means at least two chip enables are
needed to address the standard 16-bit (0–FFFFh) address range.
Note 2: When the ROM is enabled, the default memory map is reconfigured to 2MB per CE, P4CNT.5-3 = 101b, and CE4–CE7 are enabled,
P6CNT.2-0 = 111b.
Note 3: The default P4CNT.5-3 = 111b setting (4MB accessible per CE) requires only four chip enables to access the maximum 24-bit (0–
FFFFFFh) address range.
External Data Memory Addressing
Using a similar implementation as was used to expand program memory access, the DS80C400 allows up to 4MB
of data memory access through four peripheral chip enables (PCE). The Port 5 control register (P5CNT; A2h) and
Port 6 control register (P6CNT; B2h) designate the number of peripheral chip enables and the maximum amount of
addressable data memory per peripheral chip enable. Table 5 shows which port pins are converted to peripheral
chip enables, along with the maximum memory accessible through each peripheral chip enable for P5CNT, P6CNT
bit settings.
Table 5. Peripheral Chip-Enable Generation
P5CNT.2–0
000 (default)
100
101
110
111
P5.7
I/O
I/O
I/O
I/O
PCE3
P5.6
I/O
I/O
I/O
PCE2
PCE2
P5.5
I/O
I/O
PCE1
PCE1
PCE1
P5.4
I/O
PCE0
PCE0
PCE0
PCE0
P6CNT.5–3
000 (default)
001
010
011
100
MAX MEMORY ACSESSIBLE per PCE
32kB
128kB
256kB
512kB
1MB
Demultiplexed External Memory Addressing
On power-up or following any reset, the DS80C400 defaults to the traditional 8051 external memory interface, with
the address MSB presented on Port 2 and the address LSB and data multiplexed on Port 0. The multiplexed mode
requires an external latch to demultiplex the address LSB and data. The DS80C400 provides an external pin (MUX)
that, when pulled high during a power-on reset, demultiplexes the address LSB and data. If demultiplexed mode is
enabled, the address LSB is provided on Port 7 and the data on Port 0. At the expense of consuming Port 7,
demultiplexed mode eliminates the external demultiplexing latch and the delay element associated with the latch. In
some cases, the removal of this timing delay allows use of slower, less expensive external memory devices.
Table 6 shows pin assignments for the multiplexed (traditional 8051) and demultiplexed external addressing
modes.
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