DS80C400_07 Datasheet, PDF (5/97 Pages) Maxim Integrated Products – Network Microcontroller

DS80C400 Network Microcontroller
PARAMETER
SYMBOL
Data Float After RD (P3.7 or
PSEN) High
t_RHDZ
ALE Low to Valid Data In
t_LLDV
Port 0 Address to Valid Data
In
t_AVDV0
Port 2, 4, 6 Address, Port 4
CE, or Port 5 PCE to Valid
Data In
t_AVDV2
ALE Low to (RD or PSEN) or
WR Low
t_LLWL
Port 0 Address to (RD or
PSEN) or WR Low
Port 2, 4 Address, Port 4 CE,
Port 5 PCE, to (RD or PSEN)
or WR Low
Data Valid to WR Transition
t_AVWL0
t_AVWL2
t_QVWX
Data Hold After WR High
t_WHQX
RD Low to Address Float
(RD or PSEN) or WR High to
ALE
(RD or PSEN) or WR High to
Port 4 CE or Port 5 PCE
High
t_RLAZ
t_WHLH
t_WHLH2
MIN
MAX
t_CLCH - 3
t_CLCL - 3
5t_CLCL - 3
t_CLCL - 5
2t_CLCL - 6
10t_CLCL - 6
t_CLCL + t_CLCH - 5
2t_CLCL + t_CLCH - 5
10t_CLCL + t_CLCH - 5
0
t_CLCL - 4
2_CLCL - 7
6t_CLCL - 7
0
t_CLCL - 3
5t_CLCL - 3
t_CHCL -5
t_CLCL + t_CHCL - 5
5t_CLCL + t_CHCL - 5
t_CLCL - 5
2t_CLCL - 5
6t_CLCL - 5
2t_CLCL + t_CLCH - 19
(4 x C_ST + 1) t_CLCL - 19
(4 x C_ST + 5) t_CLCL - 19
3t_CLCL - 19
(4 x C_ST + 2)t_CLCL - 19
(4 x C_ST + 10)t_CLCL - 19
3t_CLCL + t_CLCH - 19
(4 x C_ST + 2)t_CLCL + t_CLCH -
19
(4 x C_ST + 10)t_CLCL + t_CLCH -
20
t_CLCH + 6
t_CLCL + 6
5t_CLCL + 6
(Note 2)
7
t_CLCL + 4
5t_CLCL + 4
t_CHCL + 13
t_CLCL + t_CHCL + 13
5t_CLCL + t_CHCL + 13
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
STRETCH VALUES
C_ST (MD2:0)
C_ST = 0
1≤ C_ST ≤ 3
4 ≤ C_ST ≤ 7
C_ST = 0
1≤ C_ST ≤ 3
4 ≤ C_ST ≤ 7
C_ST = 0
1≤ C_ST ≤ 3
4 ≤ C_ST ≤ 7
C_ST = 0
1≤ C_ST ≤ 3
4 ≤ C_ST ≤ 7
C_ST = 0
1 ≤ C_ST ≤ 3
4 ≤ C_ST ≤ 7
C_ST = 0
1 ≤ C_ST ≤ 3
4 ≤ C_ST ≤ 7
C_ST = 0
1 ≤ C_ST ≤ 3
4 ≤ C_ST ≤ 7
C_ST = 0
1 ≤ C_ST ≤ 3
4 ≤ C_ST ≤ 7
0≤ C_ST ≤ 7
C_ST = 0
1 ≤ C_ST ≤ 3
4 ≤ C_ST ≤ 7
C_ST = 0
1 ≤ C_ST ≤ 3
4 ≤ C_ST ≤ 7
Note 1: Specifications to -40°C are guaranteed by design and not production tested.
Note 2: For a MOVX read operation, on the falling edge of ALE, Port 0 is held by a weak latch until overdriven by external memory.
Note 3: All parameters apply to both commercial and industrial temperature operation, unless otherwise noted.
Note 4: CST is the stretch cycle value as determined by the MD2, MD1, and MD0 bits of the CKCON register. t_CLCL , t_CLCH , t_CHCL are time
periods associated with the internal system clock and are related to the external clock. See the System Clock Time Periods table.
Note 5: All signals characterized with load capacitance of 80pF except Port 0, Port 2, ALE, PSEN, RD, and WR with 100pF. The following
signals, when configured for memory interface, are also characterized with 100pF loading: Port 4 (CE0-3, A16–A19), Port 5.4–5.7
(PCE0-3), Port 6.0–6.5 (CE4-7, A20, A21), Port 7 (demultiplexed mode A0–A7).
Note 6: References to the XTAL, XTAL1, or CLK signal in timing diagrams are to assist in determining the relative occurrence of events, not for
determing absolute signal timing with respect to the external clock.
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