DS80C400_07 Datasheet, PDF (3/97 Pages) Maxim Integrated Products – Network Microcontroller

DS80C400 Network Microcontroller
most applications, but should be considered when proper operation must be maintained at all times. For these applications, it may be
desirable to use a more accurate external reset.
Note 3: While the specifications for V_PFW3 and V_RST3 overlap, the design of the hardware makes it such that this is not possible. Within the ranges
given, there is a guaranteed separation between these two voltages.
Note 4: Current measured with 75MHz clock source on XTAL1, V_CC3 = 3.6V, V_CC1 = 2.0V, EA and RST = 0V, Port0 = V_CC3, all other pins
disconnected.
Note 5: While the specifications for V_PFW1 and V_RST1 overlap, the design of the hardware makes it such that this is not possible. Within the ranges
given, there will be a guaranteed separation between these two voltages.
Note 6: Certain pins exhibit stronger drive capability when being used to address external memory. These pins and associated memory
interface function (in parentheses) are as follows: Port 3.6-3.7 (WR, RD), Port 4 (CE0-3, A16-A19), Port 5.4-5.7 (PCE0-3), Port 6.0-6.5
(CE4-7, A20, A21), Port 7 (demultiplexed mode A0-A7).
Note 7: This measurement reflects the weak I/O pullup state that persists following the momentary strong 0 to 1 port pin drive (V_OH2). This I/O
pin state can be achieved by applying RST = V_CC3.
Note 8: The measurement reflects the momentary strong port pin drive during a 0-to-1 transition in I/O mode. During this period, a one shot
circuit drives the ports hard for two clock cycles. A weak pullup device (V_OH1) remains in effect following the strong two-clock cycle
drive. If a port 4 or 6 pin is functioning in memory mode with pin state of 0 and the SFR bit contains a 1, changing the pin to an I/O
mode (by writing to P4CNT, for example) does not enable the two-cycle strong pullup.
Note 9: Port 3 pins 3.6 (WR) and 3.7(RD) have a stronger than normal pullup drive for only one system clock period following the transition of
either WR or RD from a 0 to a 1.
Note 10: This is the current required from an external circuit to hold a logic low level on an I/O pin while the corresponding port latch bit is set to
1. This is only the current required to hold the low level; transitions from 1 to 0 on an I/O pin also have to overcome the transition
current.
Note 11: Following the 0 to 1 one-shot timeout, ports in I/O mode source transition current when being pulled down externally. It reaches a
maximum at approximately 2V.
Note 12: During external addressing mode, weak latches are used to maintain the previously driven state on the pin until such time that the Port
0 pin is driven by an external memory source.
Note 13: The OW pin (when configured to output a 1) at V_IN = 5.5V, EA, MUX, and all MII inputs (TXCLk, RXCLk, RX_DV, RX_ER, RXD[3:0],
CRS, COL, MDIO) at V_IN = 3.6V.
AC ELECTRICAL CHARACTERISTICS (MULTIPLEXED ADDRESS/DATA BUS)
(Note 1)
(V_CC3 = 3.0V to 3.6V, V_CC1 = 1.8V ±10%, T_A = -40°C to +85°C.)
PARAMETER
External Crystal Frequency
Clock Mutliplier 2X Mode
Clock Multiplier 4X Mode
SYMBOL
1 / t_CLK
75MHz
MIN MAX
External Clock Oscillator Frequency
Clock Mutliplier 2X Mode
Clock Multiplier 4X Mode
ALE Pulse Width
Port 0 Instruction Address Valid to ALE Low
Address Hold After ALE Low
ALE Low to Valid Instruction In
ALE Low to PSEN Low
PSEN Pulse Width
PSEN Low to Valid Instruction In
Input Instruction Hold After PSEN
Input Instruction Float After PSEN
Port 0 Address to Valid Instruction In
Port 2, 4, 6 Address or Port 4 CE to Valid
Instruction In
PSEN Low to Address Float
1 / t_CLK
t_LHLL
t_AVLL
t_LLAX
t_LLIV
t_LLPL
t_PLPH
t_PLIV
t_PXIX
t_AVIV0
t_AVIV2
t_PLAZ
15.0
1.7
4.7
14.3
3.7
21.7
9.7
0
8.3
21.0
27.7
0
VARIABLE CLOCK
MIN
MAX
4
40
16
37.5
11
18.75
DC
75
16
37.5
11
18.75
t_CLCL + t_CHCL - 5
t_CHCL - 5
t_CLCH - 2
t_CLCH - 3
2t_CLCL + t_CLCH - 19
2t_CLCL - 5
2t_CLCL -17
0
t_CLCL - 5
3t_CLCL - 19
3t_CLCL + t_CLCH - 19
0
UNITS
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1: Specifications to -40°C are guaranteed by design and not production tested.
Note 2: All parameters apply to both commercial and industrial temperature operation, unless otherwise noted.
Note 3: t_CLCL, t_CLCH, t_CHCL are time periods associated with the internal system clock and are related to the external clock (t_CLK) as defined in the
External Clock Oscillator (XTAL1) Characteristics table.
Note 4: The precalculated 75MHz MIN/MAX timing specifications assume an exact 50% duty cycle.
Note 5: All signals guaranteed with load capacitance of 80pF except Port 0, Port 2, ALE, PSEN, RD, and WR with 100pF. The following signals,
when configured for memory interface, are also characterized with 100pF loading: Port 4 (CE0-3, A16–A19), Port 5.4–5.7 ( PCE0-3),
Port 6.0–6.5 (CE4-7, A20, A21), Port 7 (demultiplexed mode A0–A7).
Note 6: For high-frequency operation, special attention should be paid to the float times of the interfaced memory devices so as to avoid bus
contention.
Note 7: References to the XTAL, XTAL1 or CLK signal in timing diagrams is to assist in determining the relative occurrence of events, not for
determing absolute signal timing with respect to the external clock.
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