DS80C400_07 Datasheet, PDF (43/97 Pages) Maxim Integrated Products – Network Microcontroller

DS80C400 Network Microcontroller
Table 6. External Memory Addressing Pin Assignments
ADDRESS
SIGNAL
A21
A20
A19
A18
A17
A16
A15–A8
A7–A0
MULTIPLEXED (MUX = 0)
P6.5
P6.4
P4.7
P4.6
P4.5
P4.4
P2.7–P2.0
P0.7–P0.0
DATA
D7–D0
P0.7–P0.0
CHIP ENABLES
PERIPHERAL CHIP
ENABLES
CE7
CE6
CE5
CE4
CE3
CE2
CE1
CE0
PCE3
PCE2
PCE1
PCE0
P6.3
P6.2
P6.1
P6.0
P4.3
P4.2
P4.1
P4.0
P5.7
P5.6
P5.5
P5.4
DEMULTIPLEXED (MUX = 1)
P6.5
P6.4
P4.7
P4.6
P4.5
P4.4
P2.7–P2.0
P7.7–P7.0
P0.7–P0.0
P6.3
P6.2
P6.1
P6.0
P4.3
P4.2
P4.1
P4.0
P5.7
P5.6
P5.5
P5.4
Combined Program/Data Memory Access
The DS80C400 can be configured to allow data memory access (MOVX) to the program memory area. This feature
might be useful, for example, when modifying lookup tables or supporting in-application programming of code
space. Setting any of the PDCE7-4 (MCON1.3-0) or PDCE3-0 (MCON.3-0) bits enables combined program/data
memory access and causes the corresponding chip-enable (CE) signal to function for both MOVC and MOVX
operations. When combined program/data memory access is enabled, the peripheral chip-enable (PCE) signals
previously assigned to that data memory space are disabled. Write access to combined program and data memory
blocks is controlled by the WR signal, and read access is controlled by the PSEN signal. This feature is especially
useful if the design achieves in-system reprogrammability through external flash memory, in which a single device
is accessed through both MOVC instructions (program fetch) and MOVX write operations (updates to code
memory). Figure 1 demonstrates how setting PDCE bits can alter external memory data access.
When combined program/data memory access is enabled, there is the potential to inadvertently modify code that a
user meant to leave fixed. For this reason, the DS80C400 provides the ability to write protect the first 0–16kB of
memory accessible through each of the chip enables CE3, CE2, CE1, and CE0. The write-protection feature for
each chip enable is invoked by setting the appropriate WPE3–0 (MCON2.3-0) bit. The protected range is defined
by the WPR2–0 (MCON2.6–4) bit settings as shown in Table 7. Any MOVX instructions attempting to write to a
protected area are disallowed and set the write-protected interrupt flag (WPIF–MCON2.7), causing a write-protect
interrupt if enabled.
Table 7. Write-Protection Range
MCON2.6–4
000
001
010
011
100
101
110
111
RANGE PROTECTED (kB)
0 to 2
0 to 4
0 to 6
0 to 8
0 to 10
0 to 12
0 to 14
0 to 16
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