MAX1459 Datasheet, PDF (9/24 Pages) Maxim Integrated Products – 2-Wire, 4-20mA Smart Signal Conditioner

2-Wire, 4–20mA
Smart Signal Conditioner
The offset TC DAC output is fed into the output sum-
ming junction where it is gained by approximately 2.3,
thereby increasing the offset TC correction range. The
buffered FSOTC DAC output is available at FSOTC and
is connected to ISRC via R_FTC to correct FSOTC errors.
Internal Resistors
The MAX1459 contains three internal resistors (R_ISRC,
R_FTC, and R_TEMP) optimized for common silicon PRTs.
R_ISRC (in conjunction with the FSO DAC) programs the
nominal sensor excitation current. R_FTC (in conjunction
with the FSOTC DAC) compensates the FSOTC errors.
Both R_ISRC and R_FTC have a nominal value of 100kΩ. If
external resistors are used, R_ISRC and R_FTC can be
disabled by setting the appropriate bit (address 07h
reset to zero) in the configuration register (Table 3).
R_TEMP is a high-tempco resistor with a TC of
+4600ppm/°C and a nominal resistance of 100kΩ at
+25°C. This resistor can be used with certain sensor
types that require an external temperature sensor. The
two R_TEMP terminals are available as pin 16 and pin 17
of the MAX1459.
Table 3. Configuration Register
Description
CONFIGURATION REGISTER
BIT
EEPROM
ADDRESS (hex)
DESCRIPTION
11
0B
IRO Sign, S_IRO
10
0A
IRO MSB, C2
9
09
IRO, C1
8
08
IRO LSB, C0
7
07
R_ISRC/R_FTC Selection Bit
(0 = enable internal), IRS
6
06
Reserved “0”
5
05
Temperature Sensor Selection Bit
(0 = default V_BDRIVE)
4
04
PGA Gain (MSB), A2
3
03
PGA Gain, A1
2
02
PGA Gain (LSB), A0
1
01
Offset Sign Bit, SOFF
0
00
Offset TC Sign Bit, SOTC
Internal EEPROM
The MAX1459 has a 128-bit internal EEPROM arranged
as eight 16-bit registers. The 4 uppermost bits for each
register are reserved. The internal EEPROM is used to
store the following (also shown in the memory map in
Table 4):
• Configuration register (Table 3)
• 12-bit calibration coefficients for the offset and FSO
DACs
• 12-bit compensation coefficients for the offset TC
and FSOTC DACs
• Two general-purpose registers available to the user
for storing process information such as serial num-
ber, batch date, and check sums
The EEPROM is bit addressable. Program the EEPROM
using the following steps, where the bits have address-
es from 0 to 127 (07F hex):
1) Read the entire EEPROM, and temporarily store the
reserved bits.
2) Erase the entire EEPROM, which causes all bits to
be 0 (see the ERASE EEPROM Command section).
3) Program 1 to the required bits, including the reserved
bits (see the WRITE EEPROM BIT Command section).
4) Read the whole EEPROM, either with the READ EEP-
ROM BIT or with the READ EEPROM MATRIX com-
mands (see the READ EEPROM BIT Command and
READ EEPROM MATRIX Command sections).
Configuration Register
The configuration register (Table 3) determines the
PGA gain, the polarity of the offset and offset TC coeffi-
cients, and the coarse offset correction (IRO DAC). It
also enables/disables internal resistors (R_FTC and
R_ISRC).
DAC Registers
The offset, offset TC, FSO, and FSOTC registers store
the coefficients used by their respective calibration/
compensation DACs.
Detailed Description of the Digital Lines
Chip-Select (CS) and Write-Enable (WE)
CS is used to enable OUT, control serial communica-
tion, and force an update of the configuration and DAC
registers:
• A low on CS disables serial communication and
places OUT in a high-impedance state.
• A transition from low to high on CS forces an update
of the configuration and DAC registers from the
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