MAX1459 Datasheet, PDF (13/24 Pages) Maxim Integrated Products – 2-Wire, 4-20mA Smart Signal Conditioner

2-Wire, 4–20mA
Smart Signal Conditioner
addition, the EEPROM should only be written to at T_A =
+25°C and V_DD = +5V.
Writing to the internal EEPROM is a time-consuming
process and should only be done once. All calibra-
tion/compensation coefficients are determined by writ-
ing directly to the configuration and DAC registers. Use
the following procedure to write these calibration/com-
pensation coefficients to the EEPROM:
1) Initiate the No-OP command (0000 hex).
2) Initiate the ERASE EEPROM command (1000 hex).
3) Wait 10ms.
4) Initiate the No-OP command (0000 hex).
5) Initiate the No-OP command, with address of bit in
the data field (00XX hex), where XX is the bit
address in the data field.
6) Initiate the WRITE EEPROM BIT command, with the
same bit address in the data field (20XX hex).
7) Wait 10ms.
8) Initiate the No-OP command, with the same bit
address in the data field (00XX hex).
9) Return to step 5 until all necessary bits have been set.
10) Read EEPROM to verify that the correct calibration/
compensation coefficients have been stored.
READ EEPROM BIT Command (3 hex)
The READ EEPROM BIT command returns the bit
stored at the memory location addressed by the lower
7 bits of the data field (D6–D0). The higher bits of the
data field are ignored. Note that after a read command
has been issued, the DIO lines become an output and
the contents of the addressed EEPROM location will be
available on DIO for the next 15 cycles of SCLK. On the
falling edge of the 16th SCLK cycle after issuing the
READ EEPROM command, DIO returns to input mode
(Figure 9). DIO is stable on the rising edge of SCLK.
Writing to the Configuration, DAC, and
Output Select Registers
(Commands 8, 9, A, B, C, and D hex)
Commands 8 hex, 9 hex, A hex, B hex, and C hex write
the 12 bits of the data field (D11–D0) directly to the
configuration and DAC registers. These commands
must be followed by the LOAD REGISTER command
(Fxxx hex). Note that all four DACs and the configura-
tion register can be updated without toggling the CS
line after a valid INIT SEQUENCE (Figure 10).
OUTPUT SELECT Command (D hex)
The OUTPUT SELECT command switches the output
pin to other internal nodes instead of the default PGA
output (Figure 10). Table 6 lists the output mux settings.
SCLK
COMMAND
DATA
MSB
LSB MSB
LSB
DIO 0 0 1 0 0 0 0 0 0 A6 A5 A4 A3 A2 A1 A0
16-BIT CONTROL WORD - WRITE EEPROM BIT COMMAND (20XX HEX)
MSB
LSB
Figure 8. WRITE EEPROM BIT Command Timing Diagram
SCLK
16 CLOCK CYCLES
15 CLOCK CYCLES
16 CLOCK
CYCLES
COMMAND
MSB
LSB MSB
DATA
LSB
DIO 0 0 1 1 0 0 0 0 0 D6 D5 D4 D3 D2 D1 D0
DIO IS AN OUTPUT
PIN
EE BIT DATA
X CM3 CM2 D0
16-BIT CONTROL WORD - READ EEPROM BIT COMMAND (30XX HEX)
MSB
LSB
CONTROL
WORD
Figure 9. Timing Diagram for READ EEPROM BIT
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