MAX1459 Datasheet, PDF (7/24 Pages) Maxim Integrated Products – 2-Wire, 4-20mA Smart Signal Conditioner

2-Wire, 4–20mA
Smart Signal Conditioner
V_DD
V_DD
FSO
DAC
I = I_ISRC AA ≈ 12I_ISRC = I_BDRIVE
I_SRC
BDRIVE
FSOTC
DAC
FSOTC
R_FTC
R_ISRC
EXTERNAL
SENSOR
Figure 2. Bridge Excitation Circuit
1.25% V_DD
IRO
DAC
INP
INM
BDRIVE
OFFTC
DAC
SOTC
A2 A1 A0
A = 2.3
±
Σ
PGA
Σ
OUT
A=1
A = 2.3
±
V_DD
OFFSET
DAC
SOFF
Figure 3. Signal-Path Block Diagram
age is fed into the PGA. The 3-bit (plus sign) input-
referred offset DAC (IRO DAC) generates the coarse
offset-correction voltage. The DAC voltage reference is
1.25% of V_DD; thus, a V_DD of 5V results in a front-end
offset-correction voltage ranging from -63mV to +63mV,
in 9mV steps (Table 1). To add an offset to the input
signal, set the IRO sign bit high; to subtract an offset
from the input signal, set the IRO sign bit low. The IRO
DAC bits (C2, C1, C0, and IRO sign bit) are pro-
grammed in the configuration register (see Internal
EEPROM section).
Programmable-Gain Amplifier
The programmable-gain amplifier (PGA), which is used
to set the coarse FSO, uses a switched-capacitor
CMOS technology and contains eight selectable gain
levels from 41 to 230, in increments of 27 (Table 2). The
output of the PGA is fed to the output summing junc-
tion. The three PGA gain bits A2, A1, and A0 are stored
in the configuration register.
Output Summing Junction
The third stage in the analog signal path consists of a
summing junction for the PGA output, offset correction,
and the offset TC correction. Both the offset and the off-
set TC correction voltages are gained by a factor of 2.3
before being fed into the summing junction, increasing
the offset and offset TC correction range. The offset sign
bit and offset TC sign bit are stored in the configuration
register. The offset sign bit determines whether the off-
set correction voltage is added to (sign bit is high) or
subtracted from (sign bit is low) the PGA output.
Negative offset TC errors require a logic high for the off-
set TC sign bit. Alternately, positive offset TC errors dic-
tate a logic low for the offset TC sign bit. The output of
the summing junction is fed to the output buffer.
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