MAX1459 Datasheet, PDF (14/24 Pages) Maxim Integrated Products – 2-Wire, 4-20mA Smart Signal Conditioner

2-Wire, 4–20mA
Smart Signal Conditioner
Table 6. Output Mux Selection
MUX
VALUE
D1
0 (default
power-up)
0
1
0
2
1
3
1
D0
OUTPUT
0
Conditioned Output Voltage
(PGA)
1 Sensor Bridge Voltage (V_B)
0 Current-Source Voltage (V_SPAN)
1 Power Supply Voltage (V_DD)
The output mux facilitates the test system to monitor dif-
ferent voltages through the output pin.
READ EEPROM MATRIX Command (E hex)
The contents of the entire 128-bit EEPROM is available
on DIO upon issuing this command. Once the
MAX1459 receives the READ EEPROM MATRIX com-
mand, DIO turns into an output for the next 128 clock
cycles. After the 128th clock cycle, DIO returns to its
default input mode and the MAX1459 is ready to
accept new commands (Figure 11). Data on DIO
changes on falling edges of SCLK and is stable on ris-
ing edges of SCLK.
The EEPROM data on DIO is eight 16-bit words, MSB to
LSB. The sequence is then 0F hex, 0E hex, 0D hex, …,
00 hex (word 0), 1F hex, 1E hex, 1D hex, … (word 1),
…, 7F hex, 7E hex, …, 70 hex (word 7).
__________Applications Information
At power-up, the following occurs:
Power-Up
1) The DAC and configuration registers are reset to
zero.
2) CS transitions from low to high after power-up (an
internal pull-up resistor ensures that this happens if
CS is left unconnected), and the EEPROM contents
are read and processed.
3) The DAC and configuration registers are updated
either once (if WE is logic 0) or approximately 400
times per second (if WE is logic 1).
4) The MAX1459 begins accepting commands in a ser-
ial format on DIO immediately after receiving the INIT
SEQUENCE command.
The MAX1459 must be programmed for proper opera-
tion.
Compensation Procedure
The following compensation procedure was used to
obtain the results shown in Table 7 and Figure 12. It
assumes a pressure transducer with a +5V supply and
an output voltage that is ratiometric to the supply volt-
age. The desired offset voltage (V_OUT at P_MIN) is 0.5V,
and the desired FSO voltage (V_OUT(PMAX) - V_OUT(PMIN))
is 4V; thus, the FSO voltage (V_OUT at P_MAX) will be 4.5V
(Figure 1). The procedure requires a minimum of two
SCLK
COMMAND
MSB
LSB MSB
DATA
COMMAND
LSB
DATA
DIO CM3 CM2 CM1 CM0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 1 X X X X X X X X X X
8 HEX, 9 HEX, A HEX, B HEX, C HEX, OR D HEX WRITE REGISTER COMMAND
MSB
LSB MSB
16 BIT CONTROL WORD - LOAD REGISTER COMMAND (FXXX HEX)
XX
LSB
Figure 10. Timing Diagram for Write Register Operations
SCLK
16 CLOCK
CYCLES
16 CLOCK
CYCLES
16 CLOCK
CYCLES
COMMAND
MSB
LSB MSB
DATA
DIO IS AN OUTPUT PIN FOR
LSB
128 CLOCK CYCLES
DIO 1 1 1 0 X X X X X X X X X X X X 0F 0E 00 1F 1E 10 2F 2E 20
16-BIT CONTROL WORD - READ EEPROM MATRIX COMMAND (EXXX)
MSB
WORD 0
WORD 1
WORD 2
LSB MSB
LSB MSB
LSB MSB
LSB
16 CLOCK
CYCLES
16 CLOCK
CYCLES
7F 7E 70 CM3 CM2 D0
WORD 7
MSB
LSB
CONTROL
WORD
Figure 11. Timing Diagram for Reading the Entire EEPROM Content
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