MAX1459 Datasheet, PDF (10/24 Pages) Maxim Integrated Products – 2-Wire, 4-20mA Smart Signal Conditioner

2-Wire, 4–20mA
Smart Signal Conditioner
Table 4. EEPROM Memory Map
EE Address
Contents
0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 02 01 00
1000
Configuration
EE Address
Contents
1F 1E 1D 1C 1B 1A 19 18 17 16 15 14 13 12 11 10
1 0 0 1 MSB
Offset
LSB
EE Address
Contents
2F 2E 2D 2C 2B 2A 29 28 27 26 25 24 23 22 21 20
1 0 1 0 MSB
Offset TC
LSB
EE Address
Contents
3F 3E 3D 3C 3B 3A 39 38 37 36 35 34 33 32 31 30
1 0 1 1 MSB
FSO
LSB
EE Address
Contents
4F 4E 4D 4C 4B 4A 49 48 47 46 45 44 43 42 41 40
1 1 0 0 MSB
FSOTC
LSB
Reserved
5F 5E 5D 5C 5B 5A 59 58 57 56 55 54 53 52 51 50
0000
Reserved
EE Address
Contents
6F 6E 6D 6C 6B 6A 69 68 67 66 65 64 63 62 61 60
0000
User-Defined Bits
EE Address
Contents
7F 7E 7D 7C 7B 7A 79 78 77 76 75 74 73 72 71 70
0000
User-Defined Bits
= Reserved Bits
Note: The MAX1459 processes the Reserved Bits in the EEPROM. If these bits are not properly programmed, the configuration
and DAC registers will not be updated correctly.
EEPROM when the U bit of the INIT sequence is
zero.
• A transition from high to low on CS terminates pro-
gramming mode.
• A logic high on CS enables OUT and serial commu-
nication (see Communication Protocol section).
WE controls the refresh rate for the internal configura-
tion and DAC registers from the EEPROM and enables
the erase/write operations. If communication has been
initiated (see Communication Protocol section), internal
register refresh is disabled.
• A low on WE disables the erase/write operations and
also disables register refreshing from the EEPROM.
• A high on WE selects a refresh rate of approximately
400 times per second and enables EEPROM
erase/write operations.
• It is recommended that WE be connected to V_SS
after the MAX1459 EEPROM has been programmed.
SCLK (Serial Clock)
SCLK must be driven externally and is used to input
commands to the MAX1459 or program the internal
EEPROM contents. Input data on DIO is latched on the
rising edge of SCLK.
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