MAX1422 Datasheet, PDF (9/15 Pages) Maxim Integrated Products – 12-Bit, 20Msps, 3.3V, Low-Power ADC with Internal Reference

12-Bit, 20Msps, 3.3V, Low-Power ADC with
Internal Reference
Input Track-and-Hold
Transconductance Circuit
Figure 2 displays a simplified functional diagram of the
input track-and-hold (T/H) circuit in both track-and-hold
mode. In track mode, switches S1, S2a, S2b, S4a, S4b,
S5a, and S5b are closed. The fully differential circuit
samples the input signal onto the two capacitors (C2a
and C2b) through-switches (S4a and S4b). Switches S2a
and S2b set the common mode for the transconduc-
tance amplifier (OTA) input and open simultaneously
with S1, sampling the input waveform. The resulting
differential voltage is held on capacitors C2a and C2b.
Switches S4a and S4b, are then opened before switches
S3a and S3b connect capacitors C1a and C1b to the
output of the amplifier, and switch S4c is closed. The
OTA is used to charge capacitors, C1a and C1b, to the
same values originally held on C2a and C2b. This value
is then presented to the first stage quantizer and isolates
the pipeline from the fast-changing input. The wide input
bandwidth, T/H amplifier allows the MAX1422 to track
and sample/hold analog inputs of high frequencies
beyond Nyquist. The analog inputs INP and INN can be
driven either differentially or single-ended. Match the
impedance of INP and INN and set the common-mode
voltage to midsupply (AV_DD/2) for optimum perfor-
mance.
Analog Input and Reference Configuration
The full-scale range of the MAX1422 is determined by the
internally generated voltage difference between REFP
(AV_DD/2 + V_REFIN/4) and REFN (AV_DD/2 - V_REFIN/4). The
MAX1422’s full-scale range is adjustable through REFIN,
which provides a high input impedance for this purpose.
REFP, CML (AV_DD/2), and REFN are internally buffered,
low impedance outputs.
The MAX1422 provides three modes of reference oper-
ation:
• Internal reference mode
• Buffered external reference mode
• Unbuffered external reference mode
In internal reference mode, the on-chip 2.048V
bandgap reference is active and REFIN, REFP, CML,
and REFN, left floating. For stability purposes bypass
REFIN, REFP, REFN, and CML with a capacitor network
of 0.22µF, in parallel with a 1nF capacitor to AGND.
In buffered external reference mode, the reference volt-
age levels can be adjusted externally by applying a
stable and accurate voltage at REFIN.
In unbuffered external reference mode, REFIN is con-
nected to AGND, which deactivates the on-chip buffers
of REFP, CML, and REFN. With their buffers shut down,
MDAC
V_IN
T/H
Σ
FLASH
ADC
DAC
2 BITS
x2
V_OUT
TO NEXT
STAGE
V_IN
STAGE 1
STAGE 2
STAGE 12
DIGITAL CORRECTION LOGIC
12
D11–D0
Figure 1. Pipelined Architecture
INTERNAL
BIAS
S2a
CML
S5a
C1a
S3a
S4a
IN+
C2a
S4c
S1
IN-
S4b
C2b
S2b
INTERNAL
BIAS
Figure 2. Internal T/H Circuit
OUT
OTA
OUT
C1b
S3b
S5b
CML
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