MAX1422 Datasheet, PDF (11/15 Pages) Maxim Integrated Products – 12-Bit, 20Msps, 3.3V, Low-Power ADC with Internal Reference

12-Bit, 20Msps, 3.3V, Low-Power ADC with
Internal Reference
INP
INN
A_VDD
ADC
D11–D0
CLK
CLK
AGND
10kΩ
10kΩ
10kΩ
10kΩ
MAX1422
Figure 4. Simplified Clock Input Circuit
log portion of the MAX1421, thereby degrading its
dynamic performance. The use of digital buffers (e.g.
74LVCH16244) on the digital outputs of the ADCs can
further isolate the digital outputs from heavy capacitive
loads. To further improve the MAX1422 dynamic perfor-
mance, add small 100Ω series resistors to the digital
output paths, close to the ADC. Figure 5 displays the
timing relationship between output enable and data
output.
System Timing Requirements
Figure 6 depicts the relationship between the clock
input, analog input, and data output. The MAX1422
samples the analog input signal on the rising edge of
CLK (falling edge of CLK). and output data is valid
seven clock cycles (latency) later. Figure 6 also dis-
plays the relationship between the input clock parame-
ters and the valid output data.
Applications Information
Figure 7 depicts a typical application circuit containing
a single-ended to differential converter. The internal ref-
erence provides an AV_DD/2 output voltage for level-
shifting purposes. The input is buffered and then split
to a voltage follower and inverter. A lowpass filter at the
input suppresses some of the wideband noise associ-
ated with high-speed op amps. Select the R_ISO and
C_IN values to optimize the filter performance and to suit
a particular application. For the application in Figure 7,
a R_ISO of 50Ω is placed before the capacitive load to
prevent ringing and oscillation. The 22pF C_IN capacitor
acts as a small bypassing capacitor.Connecting C_IN
from INN to INP may further improve dynamic perfor-
mance.
OE
OUTPUT
DATA D11–D0
t_BE
HIGH-Z
VALID DATA
t_BD
HIGH-Z
Figure 5. Output Enable Timing
Table 1. MAX1422 Output Code For
Differential Inputs
DIFFERENTIAL
INPUT
VOLTAGE*
DIFFERENTIAL
INPUT
OFFSET BINARY
V_REF ✕
2047/2048
+FULL SCALE -
1LSB
V_REF ✕
2046/2048
+FULL SCALE -
2LSB
V_REF ✕ 1/2048
0
-V_REF ✕ 1/2048
-V_REF ✕
2046/2048
+1 LSB
Bipolar Zero
-1 LSB
-FULL SCALE
+1 LSB
-V_REF ✕
2047/2048
-FULL SCALE
*V_REF = V_REFP - V_REFN
1111 1111 1111
1111 1111 1110
1000 0000 0001
1000 0000 0000
0111 1111 1111
0000 0000 0001
0000 0000 0000
Using Transformer Coupling
An RF transformer (Figure 8) provides an excellent
solution to convert a single-ended signal to a fully dif-
ferential signal, required by the MAX1422 for optimum
performance. Connecting the center tap of the trans-
former to CML provides an AV_DD/2 DC level shift to the
input. Although a 1:1 transformer is shown, a 1:2 or 1:4
step-up transformer may be selected to reduce the
drive requirements.
In general, the MAX1422 provides better SFDR and
THD with fully differential input signals over single-
ended input signals, especially for very high input fre-
quencies. In differential input mode, even-order
harmonics are suppressed and each of the inputs
requires only half the signal swing compared to single-
ended mode.
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