MAX1422 Datasheet, PDF (12/15 Pages) Maxim Integrated Products – 12-Bit, 20Msps, 3.3V, Low-Power ADC with Internal Reference

12-Bit, 20Msps, 3.3V, Low-Power ADC with
Internal Reference
ANALOG INPUT
7 CLOCK-CYCLE LATENCY
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
CLK
CLK
t_DO
t_CH
t_CL
DATA OUTPUT
N-8
N-7
N-6
N-5
N-4
N-3
N-2
N-1
N
Figure 6. System and Output Timing Diagram
Single-Ended, AC-Coupled Input Signal
Figure 9 shows an AC-coupled, single-ended applica-
tion, using a MAX4108 op amp. This configuration pro-
vides high-speed, high-bandwidth, low noise, and low
distortion to maintain the integrity of the input signal.
Grounding, Bypassing and
Board Layout
The MAX1422 requires high-speed board layout design
techniques. Locate all bypass capacitors as close to
the device as possible, preferably on the same side of
the board as the ADC, using surface-mount devices for
minimum inductance. Bypass REFP, REFN, REFIN, and
CML with a parallel network of 0.22µF capacitors and
1nF to AGND. AV_DD should be bypassed with a similar
network of a 10µF bipolar capacitor in parallel with two
ceramic capacitors of 1nF and 0.1µF. Follow the same
rules to bypass the digital supply DV_DD to DGND.
Multilayer boards with separate ground and power
planes produce the highest level of signal integrity.
Consider the use of a split ground plane arrangement
to match the physical location of the analog ground
(AGND) and the digital output driver ground (DGND)
on the ADCs package. The two ground planes should
be joined at a single point such that the noisy digital
ground currents do not interfere with the analog ground
plane. Alternatively, all ground pins could share the
same ground plane if the ground plane is sufficiently
isolated from any noisy, digital systems ground plane
(e.g., downstream output buffer DSP ground plane).
Route high-speed digital signal traces away from sensi-
tive analog traces, and remove digital ground and
power planes from underneath digital outputs. Keep all
signal lines short and free of 90 degree turns.
Static Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from a straight line. This
straight-line can be either a best straight-line fit or a line
drawn between the endpoints of the transfer function,
once offset and gain errors have been nullified. The
static linearity parameters for the MAX1422 are mea-
sured using the best straight-line fit method.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an
actual step-width and the ideal value of 1LSB. A DNL
error specification of less than 1LSB guarantees no
missing codes.
Dynamic Parameter Definitions
Aperture Jitter
Figure 10 depicts the aperture jitter (t_AJ), which is the
sample-to-sample variation in the aperture delay.
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