MAX1422 Datasheet, PDF (4/15 Pages) Maxim Integrated Products – 12-Bit, 20Msps, 3.3V, Low-Power ADC with Internal Reference

12-Bit, 20Msps, 3.3V, Low-Power ADC with
Internal Reference
ELECTRICAL CHARACTERISTICS (continued)
(V_AVDD = V_DVDD = 3.3V, AGND = DGND = 0, V_IN = ±1.024V, differential input voltage at -0.5dBFS, internal reference, f_CLK = 20MHz (50%
duty cycle); digital output load C_L = 10pF, ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization.
Typical values are at T_A = +25°C.)
PARAMETER
Input Current
Input Capacitance
DIGITAL OUTPUTS (D0–D11)
SYMBOL
CLK, CLK
PD
OE
CONDITIONS
MIN TYP MAX UNITS
±330
-20
20
µA
-20
20
10
pF
Output Logic High
V_OH
I_OH = 200µA
V _{D V DD}
- 0.5
V_DVDD
V
Output Logic Low
Three-State Leakage
Three-State Capacitance
V_OL
I_OL = -200µA
0
0.5
V
-10
10
µA
2
pF
POWER REQUIREMENTS
Analog Supply Voltage
Digital Supply Voltage
Analog Supply Current
V_AVDD
V_DVDD
I_AVDD
3.138 3.3 3.465
V
2.7
3.3
3.63
V
39
46
mA
Analog Supply Current with
Internal Reference in Shutdown
V_REFIN = 0
37
44
mA
Analog Shutdown Current
Digital Supply Current
Digital Shutdown Current
Power Dissipation
Power-Supply Rejection Ratio
TIMING CHARACTERISTICS
Maximum Clock Frequency
Clock High
Clock Low
I_DVDD
P_DISS
PSRR
PD = DV_DD
PD = DV_DD
Analog power dissipation
(Note 9)
f_CLK
t_CH
t_CL
Figure 6
Figure 6, clock period 50ns
Figure 6, clock period 50ns
20
µA
3
mA
20
µA
137 152
mW
±1
mV/V
20
25
25
MHz
ns
ns
Pipeline Delay (Latency)
Figure 6
7
Clock
cycles
Aperture Delay
Aperture Jitter
Data Output Delay
Bus Enable Time
Bus Disable Time
t_AD
Figure 10
t_AJ
Figure 10
t_OD
Figure 6
t_BE
Figure 5
t_BD
Figure 5
2
ns
2
ps
5
10
14
ns
5
ns
5
ns
Note 1: Internal reference, REFIN bypassed to AGND with a combination of 0.22µF in parallel with 1nF capacitor.
Note 2: External 2.048V reference applied to REFIN.
Note 3: Internal reference disabled. VREFIN = 0, VREFP = 2.162V, VCML = 1.65V, and VREFN = 1.138V.
Note 4: IMD is measured with respect to either of the fundamental tones.
Note 5: Specifies the common-mode range of the differential input signal supplied to the MAX1422.
Note 6: VDIFF = VREFP - VREFN.
Note 7: Input bandwidth is measured at a 3dB level.
Note 8: VREFIN is internally biased to 2.048V through a 10kΩ resistor.
Note 9: Measured as the ratio of the change in mid-scale offset voltage for a ±5% change in VAVDD, using the internal reference.
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