MAX1422 Datasheet, PDF (10/15 Pages) Maxim Integrated Products – 12-Bit, 20Msps, 3.3V, Low-Power ADC with Internal Reference

12-Bit, 20Msps, 3.3V, Low-Power ADC with
Internal Reference
AV_DD
R
R
AV_DD
2
R
AV_DD
4
R
50Ω
0.22µF
MAX4284
AV_DD
2
50Ω
R ^0.22µF
MAX4284
AV_DD
4
R
50Ω
0.22µF
R
AGND
R
CML
0.1nF
REFP
0.1nF
MAX1422
REFN
0.1nF
REFIN
1V
Figure 3. Unbuffered External Reference Drive—Internal Reference Disabled
these nodes become high impedance and can be driven
by external reference sources, as shown in Figure 3.
Clock Inputs (CLK, CLK)
The MAX1422’s CLK and CLK inputs accept both sin-
gle-ended and differential input operation, and accept
CMOS-compatible clock signals. If CLK is driven with a
single-ended clock signal, bypass CLK with a 0.1µF
capacitor to AGND. Since the interstage conversion of
the device depends on the repeatability of the rising
and falling edges of the external clock, use a clock with
low jitter and fast rise and fall times (<2ns). In particu-
lar, sampling occurs on the rising edge of the clock sig-
nal, requiring this edge to have the lowest possible
jitter. Any significant aperture jitter would limit the SNR
performance of the ADC according to the following
relationship:
SNR_dB
=
20
×
log₁₀


2π
×
1
ƒ_IN
×
t
AJ


where f_IN represents the analog input frequency, and
t_AJ is the aperture jitter.
Clock jitter is especially critical for high input frequency
applications. The clock input should always be consid-
ered as an analog input and routed away from any ana-
log or digital signal lines.
The MAX1422 clock input operates with a voltage
threshold set to AV_DD/2. Clock inputs must meet the
specifications for high and low periods, as stated in the
Electrical Characteristics.
Figure 4 shows a simplified model of the clock input cir-
cuit. This circuit consists of two 10kΩ resistors to bias
the common-mode level of each input. This circuit may
be used to AC-couple the system clock signal to the
MAX1422 clock input.
Output Enable (OE), Power-Down (PD) and
Output Data (D0–D11)
With OE high, the digital outputs enter a high-imped-
ance state. If OE is held low with PD high, the outputs
are latched at the last value prior to the power-down.
All data outputs, D0 (LSB) through D11 (MSB), are
TTL/CMOS logic compatible. There is a seven clock-
cycle latency between any particular sample and its
valid output data. The output coding is in offset binary
format (Table 1).
The capacitive load on the digital outputs D0 through
D11 should be kept as low as possible (≤10pF) to avoid
large digital currents that could feed back into the ana-
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